An optimised field programmable gate array (FPGA) Jacobian logarithm architecture for turbo codes and soft bit demodulation
| Main Author: | |
|---|---|
| Format: | Thesis (University of Nottingham only) |
| Language: | English |
| Published: |
2019
|
| Subjects: | |
| Online Access: | https://eprints.nottingham.ac.uk/55716/ |
| _version_ | 1848799202387165184 |
|---|---|
| author | Lim, Li Li |
| author_facet | Lim, Li Li |
| author_sort | Lim, Li Li |
| building | Nottingham Research Data Repository |
| collection | Online Access |
| first_indexed | 2025-11-14T20:31:55Z |
| format | Thesis (University of Nottingham only) |
| id | nottingham-55716 |
| institution | University of Nottingham Malaysia Campus |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-14T20:31:55Z |
| publishDate | 2019 |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | nottingham-557162025-02-28T14:19:34Z https://eprints.nottingham.ac.uk/55716/ An optimised field programmable gate array (FPGA) Jacobian logarithm architecture for turbo codes and soft bit demodulation Lim, Li Li 2019-02-23 Thesis (University of Nottingham only) NonPeerReviewed application/pdf en arr https://eprints.nottingham.ac.uk/55716/1/LLL_Thesis_MINORCORRECTION_NOV18.pdf Lim, Li Li (2019) An optimised field programmable gate array (FPGA) Jacobian logarithm architecture for turbo codes and soft bit demodulation. PhD thesis, University of Nottingham. field programmable gate array Jacobian logarithm |
| spellingShingle | field programmable gate array Jacobian logarithm Lim, Li Li An optimised field programmable gate array (FPGA) Jacobian logarithm architecture for turbo codes and soft bit demodulation |
| title | An optimised field programmable gate array (FPGA) Jacobian logarithm architecture for turbo codes and soft bit demodulation |
| title_full | An optimised field programmable gate array (FPGA) Jacobian logarithm architecture for turbo codes and soft bit demodulation |
| title_fullStr | An optimised field programmable gate array (FPGA) Jacobian logarithm architecture for turbo codes and soft bit demodulation |
| title_full_unstemmed | An optimised field programmable gate array (FPGA) Jacobian logarithm architecture for turbo codes and soft bit demodulation |
| title_short | An optimised field programmable gate array (FPGA) Jacobian logarithm architecture for turbo codes and soft bit demodulation |
| title_sort | optimised field programmable gate array (fpga) jacobian logarithm architecture for turbo codes and soft bit demodulation |
| topic | field programmable gate array Jacobian logarithm |
| url | https://eprints.nottingham.ac.uk/55716/ |