Massively-parallel and concurrent SVM architectures - Phear, P. B. A. (2018)
This work presents several Support Vector Machine (SVM) architectures developed by the Author with the intent of exploiting the inherent parallel structures and potential- concurrency underpinning the SVM’s mathematical operation. Two SVM training sub- system prototypes are presented - a brute-force search classification training architecture, and, Artificial Neural Network (ANN)-mapped optimisation architectures for both SVM classification training and SVM regression training. This work also proposes and proto- types a set of parallelised SVM Digital Signal Processor (DSP) pipeline architectures. The parallelised SVM DSP pipeline architectures have been modelled in C and implemented in VHDL for the synthesis and fitting on an Altera Stratix V FPGA. Each system pre- sented in this work has been applied to a problem domain application appropriate to the SVM system’s architectural limitations - including the novel application of the SVM as a chaotic and non-linear system parameter-identification tool.