Low-complexity, low-area computer architectures for cryptographic application in resource constrained environments
RCE (Resource Constrained Environment) is known for its stringent hardware design requirements. With the rise of Internet of Things (IoT), low-complexity and low-area designs are becoming prominent in the face of complex security threats. Two low-complexity, low-area cryptographic processors based o...
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| Format: | Thesis (University of Nottingham only) |
| Language: | English |
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2018
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| Online Access: | https://eprints.nottingham.ac.uk/45394/ |
| _version_ | 1848797122008186880 |
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| author | Kong, Jia Hao |
| author_facet | Kong, Jia Hao |
| author_sort | Kong, Jia Hao |
| building | Nottingham Research Data Repository |
| collection | Online Access |
| description | RCE (Resource Constrained Environment) is known for its stringent hardware design requirements. With the rise of Internet of Things (IoT), low-complexity and low-area designs are becoming prominent in the face of complex security threats. Two low-complexity, low-area cryptographic processors based on the ultimate reduced instruction set computer (URISC) are created to provide security features for wireless visual sensor networks (WVSN) by using field-programmable gate array (FPGA) based visual processors typically used in RCEs. The first processor is the Two Instruction Set Computer (TISC) running the Skipjack cipher. To improve security, a Compact Instruction Set Architecture (CISA) processor running the full AES with modified S-Box was created. The modified S-Box achieved a gate count reduction of 23% with no functional compromise compared to Boyar’s. Using the Spartan-3L XC3S1500L-4-FG320 FPGA, the implementation of the TISC occupies 71 slices and 1 block RAM. The TISC achieved a throughput of 46.38 kbps at a stable 24MHz clock. The CISA which occupies 157 slices and 1 block RAM, achieved a throughput of 119.3 kbps at a stable 24MHz clock.
The CISA processor is demonstrated in two main applications, the first in a multilevel, multi cipher architecture (MMA) with two modes of operation, (1) by selecting cipher programs (primitives) and sharing crypto-blocks, (2) by using simple authentication, key renewal schemes, and showing perceptual improvements over direct AES on images. The second application demonstrates the use of the CISA processor as part of a selective encryption architecture (SEA) in combination with the millions instructions per second set partitioning in hierarchical trees (MIPS SPIHT) visual processor. The SEA is implemented on a Celoxica RC203 Vertex XC2V3000 FPGA occupying 6251 slices and a visual sensor is used to capture real world images. Four images frames were captured from a camera sensor, compressed, selectively encrypted, and sent over to a PC environment for decryption. The final design emulates a working visual sensor, from on node processing and encryption to back-end data processing on a server computer. |
| first_indexed | 2025-11-14T19:58:51Z |
| format | Thesis (University of Nottingham only) |
| id | nottingham-45394 |
| institution | University of Nottingham Malaysia Campus |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-14T19:58:51Z |
| publishDate | 2018 |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | nottingham-453942025-02-28T11:58:42Z https://eprints.nottingham.ac.uk/45394/ Low-complexity, low-area computer architectures for cryptographic application in resource constrained environments Kong, Jia Hao RCE (Resource Constrained Environment) is known for its stringent hardware design requirements. With the rise of Internet of Things (IoT), low-complexity and low-area designs are becoming prominent in the face of complex security threats. Two low-complexity, low-area cryptographic processors based on the ultimate reduced instruction set computer (URISC) are created to provide security features for wireless visual sensor networks (WVSN) by using field-programmable gate array (FPGA) based visual processors typically used in RCEs. The first processor is the Two Instruction Set Computer (TISC) running the Skipjack cipher. To improve security, a Compact Instruction Set Architecture (CISA) processor running the full AES with modified S-Box was created. The modified S-Box achieved a gate count reduction of 23% with no functional compromise compared to Boyar’s. Using the Spartan-3L XC3S1500L-4-FG320 FPGA, the implementation of the TISC occupies 71 slices and 1 block RAM. The TISC achieved a throughput of 46.38 kbps at a stable 24MHz clock. The CISA which occupies 157 slices and 1 block RAM, achieved a throughput of 119.3 kbps at a stable 24MHz clock. The CISA processor is demonstrated in two main applications, the first in a multilevel, multi cipher architecture (MMA) with two modes of operation, (1) by selecting cipher programs (primitives) and sharing crypto-blocks, (2) by using simple authentication, key renewal schemes, and showing perceptual improvements over direct AES on images. The second application demonstrates the use of the CISA processor as part of a selective encryption architecture (SEA) in combination with the millions instructions per second set partitioning in hierarchical trees (MIPS SPIHT) visual processor. The SEA is implemented on a Celoxica RC203 Vertex XC2V3000 FPGA occupying 6251 slices and a visual sensor is used to capture real world images. Four images frames were captured from a camera sensor, compressed, selectively encrypted, and sent over to a PC environment for decryption. The final design emulates a working visual sensor, from on node processing and encryption to back-end data processing on a server computer. 2018-02-24 Thesis (University of Nottingham only) NonPeerReviewed application/pdf en arr https://eprints.nottingham.ac.uk/45394/1/PHD%20Thesis%202017%20-%20final.pdf Kong, Jia Hao (2018) Low-complexity, low-area computer architectures for cryptographic application in resource constrained environments. PhD thesis, University of Nottingham. resource constrained environment cryptographic integrated circuits computer-aided design |
| spellingShingle | resource constrained environment cryptographic integrated circuits computer-aided design Kong, Jia Hao Low-complexity, low-area computer architectures for cryptographic application in resource constrained environments |
| title | Low-complexity, low-area computer architectures for cryptographic application in resource constrained environments |
| title_full | Low-complexity, low-area computer architectures for cryptographic application in resource constrained environments |
| title_fullStr | Low-complexity, low-area computer architectures for cryptographic application in resource constrained environments |
| title_full_unstemmed | Low-complexity, low-area computer architectures for cryptographic application in resource constrained environments |
| title_short | Low-complexity, low-area computer architectures for cryptographic application in resource constrained environments |
| title_sort | low-complexity, low-area computer architectures for cryptographic application in resource constrained environments |
| topic | resource constrained environment cryptographic integrated circuits computer-aided design |
| url | https://eprints.nottingham.ac.uk/45394/ |