RISC Design: Synthesis Of The MIPS Processor Core

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RISC Design: Synthesis Of The MIPS Processor Core

The idea of this project was to create a microprocessor as a building block in VHDL that later easily can be included in a larger design. MIPS (Microprocessor without Interlocked Pipeline Stages) is an example of a modern RISC (Reduced Instruction Set Computer) had been chosen for this project base...

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Bibliographic Details
Main Author:	Yew, Teong Guan
Format:	Thesis
Published:	2003
Subjects:	QA76.75-76.765 Computer software
Online Access:	http://shdl.mmu.edu.my/951/

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