RISC Design: Synthesis Of The MIPS Processor Core - Yew, Teong Guan (2003)
The idea of this project was to create a microprocessor as a building block in VHDL that later easily can be included in a larger design. MIPS (Microprocessor without Interlocked Pipeline Stages) is an example of a modern RISC (Reduced Instruction Set Computer) had been chosen for this project based on the simplicity of its instruction set and better performance then CISC.