RISC Design: Synthesis Of The MIPS Processor Core
The idea of this project was to create a microprocessor as a building block in VHDL that later easily can be included in a larger design. MIPS (Microprocessor without Interlocked Pipeline Stages) is an example of a modern RISC (Reduced Instruction Set Computer) had been chosen for this project base...
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| Format: | Thesis |
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2003
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| Online Access: | http://shdl.mmu.edu.my/951/ |
| _version_ | 1848789645653966848 |
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| author | Yew, Teong Guan |
| author_facet | Yew, Teong Guan |
| author_sort | Yew, Teong Guan |
| building | MMU Institutional Repository |
| collection | Online Access |
| description | The idea of this project was to create a microprocessor as a building block in VHDL that later easily can be included in a larger design. MIPS (Microprocessor without Interlocked Pipeline Stages) is an example of a modern RISC (Reduced Instruction Set Computer) had been chosen for this project based on the simplicity of its instruction set and better performance then CISC. |
| first_indexed | 2025-11-14T18:00:01Z |
| format | Thesis |
| id | mmu-951 |
| institution | Multimedia University |
| institution_category | Local University |
| last_indexed | 2025-11-14T18:00:01Z |
| publishDate | 2003 |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | mmu-9512010-07-13T03:03:37Z http://shdl.mmu.edu.my/951/ RISC Design: Synthesis Of The MIPS Processor Core Yew, Teong Guan QA76.75-76.765 Computer software The idea of this project was to create a microprocessor as a building block in VHDL that later easily can be included in a larger design. MIPS (Microprocessor without Interlocked Pipeline Stages) is an example of a modern RISC (Reduced Instruction Set Computer) had been chosen for this project based on the simplicity of its instruction set and better performance then CISC. 2003-04 Thesis NonPeerReviewed Yew, Teong Guan (2003) RISC Design: Synthesis Of The MIPS Processor Core. Masters thesis, Multimedia University. http://myto.perpun.net.my/metoalogin/logina.php |
| spellingShingle | QA76.75-76.765 Computer software Yew, Teong Guan RISC Design: Synthesis Of The MIPS Processor Core |
| title | RISC Design: Synthesis Of The MIPS Processor Core |
| title_full | RISC Design: Synthesis Of The MIPS Processor Core |
| title_fullStr | RISC Design: Synthesis Of The MIPS Processor Core |
| title_full_unstemmed | RISC Design: Synthesis Of The MIPS Processor Core |
| title_short | RISC Design: Synthesis Of The MIPS Processor Core |
| title_sort | risc design: synthesis of the mips processor core |
| topic | QA76.75-76.765 Computer software |
| url | http://shdl.mmu.edu.my/951/ http://shdl.mmu.edu.my/951/ |