Low-power fast (LPF) SRAM cell for write/read operation
Power consumption and Static noise margin (SNM) are most important parameters for memory design. The main source of power consumption in SRAM cell is due to large voltage swing on the bitlines during write operation. To reduce the power consumption and enhance the performance of the SRAM cell, we pr...
| Main Authors: | , |
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| Format: | Article |
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2011
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| Online Access: | http://shdl.mmu.edu.my/3341/ |
| _version_ | 1848790301060104192 |
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| author | Prabhu, C. M. R. Singh, Ajay Kumar |
| author_facet | Prabhu, C. M. R. Singh, Ajay Kumar |
| author_sort | Prabhu, C. M. R. |
| building | MMU Institutional Repository |
| collection | Online Access |
| description | Power consumption and Static noise margin (SNM) are most important parameters for memory design. The main source of power consumption in SRAM cell is due to large voltage swing on the bitlines during write operation. To reduce the power consumption and enhance the performance of the SRAM cell, we propose a Low-power fast (LPF) SRAM cell. The cell is simulated in terms of power, delay and read stability. The simulated result shows that the read and write power of the proposed cell is reduced up to 33% and 57.12% at 1.2V (in CMOS 0.12 mu m technology) respectively compared to the 6T cell. The read SNM of the LPF cell is 2x times of the conventional cell. |
| first_indexed | 2025-11-14T18:10:26Z |
| format | Article |
| id | mmu-3341 |
| institution | Multimedia University |
| institution_category | Local University |
| last_indexed | 2025-11-14T18:10:26Z |
| publishDate | 2011 |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | mmu-33412012-01-09T04:00:59Z http://shdl.mmu.edu.my/3341/ Low-power fast (LPF) SRAM cell for write/read operation Prabhu, C. M. R. Singh, Ajay Kumar TA Engineering (General). Civil engineering (General) Power consumption and Static noise margin (SNM) are most important parameters for memory design. The main source of power consumption in SRAM cell is due to large voltage swing on the bitlines during write operation. To reduce the power consumption and enhance the performance of the SRAM cell, we propose a Low-power fast (LPF) SRAM cell. The cell is simulated in terms of power, delay and read stability. The simulated result shows that the read and write power of the proposed cell is reduced up to 33% and 57.12% at 1.2V (in CMOS 0.12 mu m technology) respectively compared to the 6T cell. The read SNM of the LPF cell is 2x times of the conventional cell. 2011 Article PeerReviewed Prabhu, C. M. R. and Singh, Ajay Kumar (2011) Low-power fast (LPF) SRAM cell for write/read operation. IEICE Electronics Express, 8 (18). pp. 1473-1478. ISSN 1349-2543 http://dx.doi.org/10.1587/elex.8.1473 doi:10.1587/elex.8.1473 doi:10.1587/elex.8.1473 |
| spellingShingle | TA Engineering (General). Civil engineering (General) Prabhu, C. M. R. Singh, Ajay Kumar Low-power fast (LPF) SRAM cell for write/read operation |
| title | Low-power fast (LPF) SRAM cell for write/read operation |
| title_full | Low-power fast (LPF) SRAM cell for write/read operation |
| title_fullStr | Low-power fast (LPF) SRAM cell for write/read operation |
| title_full_unstemmed | Low-power fast (LPF) SRAM cell for write/read operation |
| title_short | Low-power fast (LPF) SRAM cell for write/read operation |
| title_sort | low-power fast (lpf) sram cell for write/read operation |
| topic | TA Engineering (General). Civil engineering (General) |
| url | http://shdl.mmu.edu.my/3341/ http://shdl.mmu.edu.my/3341/ http://shdl.mmu.edu.my/3341/ |