Fast-lock dual charge pump analog DLL using improved phase frequency detector

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Fast-lock dual charge pump analog DLL using improved phase frequency detector

In this paper, a dual charge pump architecture for fast-lock low-jitter analog delay-locked loop (DLL) is proposed and analyzed. The proposed fast lock analog DLL takes up less area compared to other similar fast lock analog DLL due to the reduction of the number of phase frequency detector (PFD) us...

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Bibliographic Details
Main Authors:	Lip-Kai, Soh, Sulaiman, Mohd-Shahiman, Yusoff, Zubaida
Format:	Conference or Workshop Item
Published:	2007
Subjects:	T Technology (General) QA75.5-76.95 Electronic computers. Computer science
Online Access:	http://shdl.mmu.edu.my/3282/

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