Fast-lock dual charge pump analog DLL using improved phase frequency detector
In this paper, a dual charge pump architecture for fast-lock low-jitter analog delay-locked loop (DLL) is proposed and analyzed. The proposed fast lock analog DLL takes up less area compared to other similar fast lock analog DLL due to the reduction of the number of phase frequency detector (PFD) us...
| Main Authors: | , , |
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| Format: | Conference or Workshop Item |
| Published: |
2007
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| Online Access: | http://shdl.mmu.edu.my/3282/ |
| _version_ | 1848790284536643584 |
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| author | Lip-Kai, Soh Sulaiman, Mohd-Shahiman Yusoff, Zubaida |
| author_facet | Lip-Kai, Soh Sulaiman, Mohd-Shahiman Yusoff, Zubaida |
| author_sort | Lip-Kai, Soh |
| building | MMU Institutional Repository |
| collection | Online Access |
| description | In this paper, a dual charge pump architecture for fast-lock low-jitter analog delay-locked loop (DLL) is proposed and analyzed. The proposed fast lock analog DLL takes up less area compared to other similar fast lock analog DLL due to the reduction of the number of phase frequency detector (PFD) used in the design. An improved PFD is proposed to reduce the output jitter by reducing the one-shot pulse produced when the reference signal and output signal is in phase. The proposed DLL circuit is designed based on the Silterra 0.18-mu m INNI CNIOS process with a 1.8-V supply voltage. The active area of the proposed DLL circuit is 327.46 mu m x 116.16 mu m. An experimental chip was implemented and measured. The measurement results show that the proposed DLL has fast locking and low jitter properties. |
| first_indexed | 2025-11-14T18:10:10Z |
| format | Conference or Workshop Item |
| id | mmu-3282 |
| institution | Multimedia University |
| institution_category | Local University |
| last_indexed | 2025-11-14T18:10:10Z |
| publishDate | 2007 |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | mmu-32822011-10-18T02:19:04Z http://shdl.mmu.edu.my/3282/ Fast-lock dual charge pump analog DLL using improved phase frequency detector Lip-Kai, Soh Sulaiman, Mohd-Shahiman Yusoff, Zubaida T Technology (General) QA75.5-76.95 Electronic computers. Computer science In this paper, a dual charge pump architecture for fast-lock low-jitter analog delay-locked loop (DLL) is proposed and analyzed. The proposed fast lock analog DLL takes up less area compared to other similar fast lock analog DLL due to the reduction of the number of phase frequency detector (PFD) used in the design. An improved PFD is proposed to reduce the output jitter by reducing the one-shot pulse produced when the reference signal and output signal is in phase. The proposed DLL circuit is designed based on the Silterra 0.18-mu m INNI CNIOS process with a 1.8-V supply voltage. The active area of the proposed DLL circuit is 327.46 mu m x 116.16 mu m. An experimental chip was implemented and measured. The measurement results show that the proposed DLL has fast locking and low jitter properties. 2007-04 Conference or Workshop Item NonPeerReviewed Lip-Kai, Soh and Sulaiman, Mohd-Shahiman and Yusoff, Zubaida (2007) Fast-lock dual charge pump analog DLL using improved phase frequency detector. In: International Symposium on VLSI Design, Automation and Test, 25-27 APR 2007, Hsinchu, TAIWAN. http://apps.webofknowledge.com/full_record.do?product=WOS&search_mode=GeneralSearch&qid=1&SID=Q2B3J83BDN3nFOLpEAc&page=127&doc=1270 |
| spellingShingle | T Technology (General) QA75.5-76.95 Electronic computers. Computer science Lip-Kai, Soh Sulaiman, Mohd-Shahiman Yusoff, Zubaida Fast-lock dual charge pump analog DLL using improved phase frequency detector |
| title | Fast-lock dual charge pump analog DLL using improved phase frequency detector |
| title_full | Fast-lock dual charge pump analog DLL using improved phase frequency detector |
| title_fullStr | Fast-lock dual charge pump analog DLL using improved phase frequency detector |
| title_full_unstemmed | Fast-lock dual charge pump analog DLL using improved phase frequency detector |
| title_short | Fast-lock dual charge pump analog DLL using improved phase frequency detector |
| title_sort | fast-lock dual charge pump analog dll using improved phase frequency detector |
| topic | T Technology (General) QA75.5-76.95 Electronic computers. Computer science |
| url | http://shdl.mmu.edu.my/3282/ http://shdl.mmu.edu.my/3282/ |