Low power and high speed 8x8 bit multiplier using non-clocked Pass Transistor Logic
In this paper we have analyzed an 8-bit multiplier circuit using non clocked pass gate families with help of carry save multiplier (CSA) technique. The multiplier cell of the adder is designed by using pass transistors (n-transistors), p-transistors used as cross-coupled devices. The adder cell is d...
| Main Authors: | , , |
|---|---|
| Format: | Conference or Workshop Item |
| Published: |
2007
|
| Subjects: | |
| Online Access: | http://shdl.mmu.edu.my/3161/ |