An 8-Gb/s half-rate clock and data recovery circuit - Khalek, Faizal; Sulaiman, Mohd-Shahiman; Yusoff, Zubaida (2007)
This paper presents circuit design and simulation result of the 8-Gb/s half-rate clock and data recovery circuit (CDR) by 0.18u process technology. The linear phase detector was used for the CDR and able to give linear relation of the phase error between 35ps to 110ps. While the data output jitter p-p is 4.6ps and the clock jitter p-p is 6.6ps. The power consumption is 55mW from a 1.8V voltage supply.