A fully-integrated 5 Gbit/s CMOS clock and data recovery circuit

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A fully-integrated 5 Gbit/s CMOS clock and data recovery circuit

A fully-integrated 5 Gb/s PLL-based clock and data recovery circuit based on a linear half-rate phase detector (PD) architecture is presented. Data retiming performed by the linear PD provides practically no systematic offset for the operating frequency of interest. The circuit was designed in a 0.1...

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Bibliographic Details
Main Authors:	Tan, Kok Siang, Sulaiman, Mohd Shahiman, Ibne, Mamun Reaz, Chuah, Hean Teik, Sachdev, Manoj
Format:	Article
Language:	English
Published:	Springer US 2007
Subjects:	T Technology (General) QA75.5-76.95 Electronic computers. Computer science
Online Access:	http://shdl.mmu.edu.my/3065/ http://shdl.mmu.edu.my/3065/1/1087.pdf

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