A fully-integrated 5 Gbit/s CMOS clock and data recovery circuit - Tan, Kok Siang; Sulaiman, Mohd Shahiman; Ibne, Mamun Reaz; Chuah, Hean Teik; Sachdev, Manoj (Springer US, 2007)
A fully-integrated 5 Gb/s PLL-based clock and data recovery circuit based on a linear half-rate phase detector (PD) architecture is presented. Data retiming performed by the linear PD provides practically no systematic offset for the operating frequency of interest. The circuit was designed in a 0.18 mu m CMOS process and occupies an active area of 0.2 x 0.32 mm(2). The CDR exhibits an RMS jitter of +/- 1.2 ps and a peak-to-peak jitter of 5 ps. The power dissipation is 97 mW from a 1.8 V supply.