A fully-integrated 5 Gbit/s CMOS clock and data recovery circuit
A fully-integrated 5 Gb/s PLL-based clock and data recovery circuit based on a linear half-rate phase detector (PD) architecture is presented. Data retiming performed by the linear PD provides practically no systematic offset for the operating frequency of interest. The circuit was designed in a 0.1...
| Main Authors: | , , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Springer US
2007
|
| Subjects: | |
| Online Access: | http://shdl.mmu.edu.my/3065/ http://shdl.mmu.edu.my/3065/1/1087.pdf |
| _version_ | 1848790224177463296 |
|---|---|
| author | Tan, Kok Siang Sulaiman, Mohd Shahiman Ibne, Mamun Reaz Chuah, Hean Teik Sachdev, Manoj |
| author_facet | Tan, Kok Siang Sulaiman, Mohd Shahiman Ibne, Mamun Reaz Chuah, Hean Teik Sachdev, Manoj |
| author_sort | Tan, Kok Siang |
| building | MMU Institutional Repository |
| collection | Online Access |
| description | A fully-integrated 5 Gb/s PLL-based clock and data recovery circuit based on a linear half-rate phase detector (PD) architecture is presented. Data retiming performed by the linear PD provides practically no systematic offset for the operating frequency of interest. The circuit was designed in a 0.18 mu m CMOS process and occupies an active area of 0.2 x 0.32 mm(2). The CDR exhibits an RMS jitter of +/- 1.2 ps and a peak-to-peak jitter of 5 ps. The power dissipation is 97 mW from a 1.8 V supply. |
| first_indexed | 2025-11-14T18:09:13Z |
| format | Article |
| id | mmu-3065 |
| institution | Multimedia University |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-14T18:09:13Z |
| publishDate | 2007 |
| publisher | Springer US |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | mmu-30652020-12-29T17:53:45Z http://shdl.mmu.edu.my/3065/ A fully-integrated 5 Gbit/s CMOS clock and data recovery circuit Tan, Kok Siang Sulaiman, Mohd Shahiman Ibne, Mamun Reaz Chuah, Hean Teik Sachdev, Manoj T Technology (General) QA75.5-76.95 Electronic computers. Computer science A fully-integrated 5 Gb/s PLL-based clock and data recovery circuit based on a linear half-rate phase detector (PD) architecture is presented. Data retiming performed by the linear PD provides practically no systematic offset for the operating frequency of interest. The circuit was designed in a 0.18 mu m CMOS process and occupies an active area of 0.2 x 0.32 mm(2). The CDR exhibits an RMS jitter of +/- 1.2 ps and a peak-to-peak jitter of 5 ps. The power dissipation is 97 mW from a 1.8 V supply. Springer US 2007-05 Article NonPeerReviewed text en http://shdl.mmu.edu.my/3065/1/1087.pdf Tan, Kok Siang and Sulaiman, Mohd Shahiman and Ibne, Mamun Reaz and Chuah, Hean Teik and Sachdev, Manoj (2007) A fully-integrated 5 Gbit/s CMOS clock and data recovery circuit. Analog Integrated Circuits and Signal Processing, 51 (2). 101-109 . ISSN 0925-1030, 1573-1979 http://dx.doi.org/10.1007/s10470-007-9062-8 doi:10.1007/s10470-007-9062-8 doi:10.1007/s10470-007-9062-8 |
| spellingShingle | T Technology (General) QA75.5-76.95 Electronic computers. Computer science Tan, Kok Siang Sulaiman, Mohd Shahiman Ibne, Mamun Reaz Chuah, Hean Teik Sachdev, Manoj A fully-integrated 5 Gbit/s CMOS clock and data recovery circuit |
| title | A fully-integrated 5 Gbit/s CMOS clock and data recovery circuit |
| title_full | A fully-integrated 5 Gbit/s CMOS clock and data recovery circuit |
| title_fullStr | A fully-integrated 5 Gbit/s CMOS clock and data recovery circuit |
| title_full_unstemmed | A fully-integrated 5 Gbit/s CMOS clock and data recovery circuit |
| title_short | A fully-integrated 5 Gbit/s CMOS clock and data recovery circuit |
| title_sort | fully-integrated 5 gbit/s cmos clock and data recovery circuit |
| topic | T Technology (General) QA75.5-76.95 Electronic computers. Computer science |
| url | http://shdl.mmu.edu.my/3065/ http://shdl.mmu.edu.my/3065/ http://shdl.mmu.edu.my/3065/ http://shdl.mmu.edu.my/3065/1/1087.pdf |