An Enhanced Memory Address Mapping Scheme for Improved Memory Access Performance of 2-D DWT Processing Systems
The implementation of the memory for storing image and transform coefficients in 2-D DWT processing systems using the more cost-effective external memory module such as DDR DRAM is shown to suffer from effective memory bandwidth which is significantly lower than the memory system peak bandwidth if t...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
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SPRINGER
2007
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| Online Access: | http://shdl.mmu.edu.my/3056/ http://shdl.mmu.edu.my/3056/1/1078.pdf |
| _version_ | 1848790221580140544 |
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| author | Lee, Sze-Wei Lim, Soon-Chieh |
| author_facet | Lee, Sze-Wei Lim, Soon-Chieh |
| author_sort | Lee, Sze-Wei |
| building | MMU Institutional Repository |
| collection | Online Access |
| description | The implementation of the memory for storing image and transform coefficients in 2-D DWT processing systems using the more cost-effective external memory module such as DDR DRAM is shown to suffer from effective memory bandwidth which is significantly lower than the memory system peak bandwidth if the conventional direct logical-to-physical memory address mapping is adopted. The low effective memory bandwidth is caused by the high level of memory overhead cycle occurrence which is in turn is closely related to the logical memory access patterns of 2-D DWT processes. The problem becomes even more severe for the 2-D DWT processing of video. An analysis on the logical memory access patterns of multi-level 2-D DWT is carried out and an enhanced logical-to-physical memory mapping scheme which minimizes the occurrence of memory overhead cycles is proposed. The proposed scheme is simulated and its performance in terms of effective memory access bandwidth is evaluated and compared with the conventional direct mapping scheme. |
| first_indexed | 2025-11-14T18:09:10Z |
| format | Article |
| id | mmu-3056 |
| institution | Multimedia University |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-14T18:09:10Z |
| publishDate | 2007 |
| publisher | SPRINGER |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | mmu-30562014-02-27T07:31:59Z http://shdl.mmu.edu.my/3056/ An Enhanced Memory Address Mapping Scheme for Improved Memory Access Performance of 2-D DWT Processing Systems Lee, Sze-Wei Lim, Soon-Chieh T Technology (General) QA75.5-76.95 Electronic computers. Computer science The implementation of the memory for storing image and transform coefficients in 2-D DWT processing systems using the more cost-effective external memory module such as DDR DRAM is shown to suffer from effective memory bandwidth which is significantly lower than the memory system peak bandwidth if the conventional direct logical-to-physical memory address mapping is adopted. The low effective memory bandwidth is caused by the high level of memory overhead cycle occurrence which is in turn is closely related to the logical memory access patterns of 2-D DWT processes. The problem becomes even more severe for the 2-D DWT processing of video. An analysis on the logical memory access patterns of multi-level 2-D DWT is carried out and an enhanced logical-to-physical memory mapping scheme which minimizes the occurrence of memory overhead cycles is proposed. The proposed scheme is simulated and its performance in terms of effective memory access bandwidth is evaluated and compared with the conventional direct mapping scheme. SPRINGER 2007-06 Article NonPeerReviewed text en http://shdl.mmu.edu.my/3056/1/1078.pdf Lee, Sze-Wei and Lim, Soon-Chieh (2007) An Enhanced Memory Address Mapping Scheme for Improved Memory Access Performance of 2-D DWT Processing Systems. The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, 47 (3). pp. 201-221. ISSN 0922-5773 http://dx.doi.org/10.1007/s11265-006-0042-5 doi:10.1007/s11265-006-0042-5 doi:10.1007/s11265-006-0042-5 |
| spellingShingle | T Technology (General) QA75.5-76.95 Electronic computers. Computer science Lee, Sze-Wei Lim, Soon-Chieh An Enhanced Memory Address Mapping Scheme for Improved Memory Access Performance of 2-D DWT Processing Systems |
| title | An Enhanced Memory Address Mapping Scheme for Improved Memory Access Performance of 2-D DWT Processing Systems |
| title_full | An Enhanced Memory Address Mapping Scheme for Improved Memory Access Performance of 2-D DWT Processing Systems |
| title_fullStr | An Enhanced Memory Address Mapping Scheme for Improved Memory Access Performance of 2-D DWT Processing Systems |
| title_full_unstemmed | An Enhanced Memory Address Mapping Scheme for Improved Memory Access Performance of 2-D DWT Processing Systems |
| title_short | An Enhanced Memory Address Mapping Scheme for Improved Memory Access Performance of 2-D DWT Processing Systems |
| title_sort | enhanced memory address mapping scheme for improved memory access performance of 2-d dwt processing systems |
| topic | T Technology (General) QA75.5-76.95 Electronic computers. Computer science |
| url | http://shdl.mmu.edu.my/3056/ http://shdl.mmu.edu.my/3056/ http://shdl.mmu.edu.my/3056/ http://shdl.mmu.edu.my/3056/1/1078.pdf |