Low-power dual-port asynchronous CMOS SRAM design techniques - Tan, Soon-Hwei; Loh, Poh-Yee; Mohd-Shahiman, Sulaiman; Yusoff, Zubaida (SOC MICROELECTRONICS, 2007)
This paper describes the review and short tutorial on design techniques for low-power SRAM, focusing on the design of a 1-Mb CMOS SRAM on CMOS 0.25-mu m process. The building blocks of the SRAM are individually discussed and various techniques are described, with the most appropriate one chosen for the block. SRAM power saving techniques are also described and implemented in the 1-Mb memory. The designed SRAM is simulated across different Process, Voltage, and Temperature (PVT) corners under the presence of parasitics. The performance of the 1-Mb SRAM is then compared with that of the previously published work. It is found that a minimum read access time of 4.26ns is achieved. The SRAM can operate at maximum frequency of 220MHz in dual-port mode and dissipates minimum active power of 31 mW and is able to retain data at 0.1 V supply voltage and consumes a standby power of 80nW. The SRAM occupies an area of 115mm(2).