Design of high-speed clock and data recovery circuits
This article describes the various architectures for a high-speed clock and data recovery (CDR) circuit. Following a brief introduction of clock and data recovery circuit, a phase detection circuit, one of the most critical blocks in a CDR that determines not only the performance but also the CDR ar...
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| Format: | Article |
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Springer US
2007
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| Online Access: | http://shdl.mmu.edu.my/3029/ |
| _version_ | 1848790215007666176 |
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| author | Tan, Kok Siang Sulaiman, Mohd Shahiman Chuah, Hean Teik Sachdev, Manoj |
| author_facet | Tan, Kok Siang Sulaiman, Mohd Shahiman Chuah, Hean Teik Sachdev, Manoj |
| author_sort | Tan, Kok Siang |
| building | MMU Institutional Repository |
| collection | Online Access |
| description | This article describes the various architectures for a high-speed clock and data recovery (CDR) circuit. Following a brief introduction of clock and data recovery circuit, a phase detection circuit, one of the most critical blocks in a CDR that determines not only the performance but also the CDR architecture, is addressed. The descriptions start with the most basic XOR logic up to the phase-frequency detector circuit. Trade-offs of each of the phase detectors are outlined. Two types of dual loop CDR architecture are briefly introduced. Finally, full-rate and half rate CDR architectures are described. |
| first_indexed | 2025-11-14T18:09:04Z |
| format | Article |
| id | mmu-3029 |
| institution | Multimedia University |
| institution_category | Local University |
| last_indexed | 2025-11-14T18:09:04Z |
| publishDate | 2007 |
| publisher | Springer US |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | mmu-30292020-12-29T17:25:43Z http://shdl.mmu.edu.my/3029/ Design of high-speed clock and data recovery circuits Tan, Kok Siang Sulaiman, Mohd Shahiman Chuah, Hean Teik Sachdev, Manoj T Technology (General) QA75.5-76.95 Electronic computers. Computer science This article describes the various architectures for a high-speed clock and data recovery (CDR) circuit. Following a brief introduction of clock and data recovery circuit, a phase detection circuit, one of the most critical blocks in a CDR that determines not only the performance but also the CDR architecture, is addressed. The descriptions start with the most basic XOR logic up to the phase-frequency detector circuit. Trade-offs of each of the phase detectors are outlined. Two types of dual loop CDR architecture are briefly introduced. Finally, full-rate and half rate CDR architectures are described. Springer US 2007-08 Article NonPeerReviewed Tan, Kok Siang and Sulaiman, Mohd Shahiman and Chuah, Hean Teik and Sachdev, Manoj (2007) Design of high-speed clock and data recovery circuits. Analog Integrated Circuits and Signal Processing, 52 (1-2). pp. 15-23. ISSN 0925-1030, 1573-1979 http://dx.doi.org/10.1007/s10470-007-9093-1 doi:10.1007/s10470-007-9093-1 doi:10.1007/s10470-007-9093-1 |
| spellingShingle | T Technology (General) QA75.5-76.95 Electronic computers. Computer science Tan, Kok Siang Sulaiman, Mohd Shahiman Chuah, Hean Teik Sachdev, Manoj Design of high-speed clock and data recovery circuits |
| title | Design of high-speed clock and data recovery circuits |
| title_full | Design of high-speed clock and data recovery circuits |
| title_fullStr | Design of high-speed clock and data recovery circuits |
| title_full_unstemmed | Design of high-speed clock and data recovery circuits |
| title_short | Design of high-speed clock and data recovery circuits |
| title_sort | design of high-speed clock and data recovery circuits |
| topic | T Technology (General) QA75.5-76.95 Electronic computers. Computer science |
| url | http://shdl.mmu.edu.my/3029/ http://shdl.mmu.edu.my/3029/ http://shdl.mmu.edu.my/3029/ |