Design of a low-power, high performance, 8×8bit multiplier using a Shannon-based adder cell

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Design of a low-power, high performance, 8×8bit multiplier using a Shannon-based adder cell

In this paper, we have developed a new full-adder cell using multiplexing control input techniques (MCIT) for the sum operation and the Shannon-based technique to implement the carry. The proposed adder cell is applied to the design of several 8-bit array multipliers, namely a Braun array multiplier...

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Bibliographic Details
Main Authors:	SENTHILPARI, C, SINGH, A, DIWAKAR, K
Format:	Article
Language:	English
Published:	ELSEVIER SCI LTD 2008
Subjects:	T Technology (General) QA75.5-76.95 Electronic computers. Computer science
Online Access:	http://shdl.mmu.edu.my/2744/ http://shdl.mmu.edu.my/2744/1/784.pdf

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