APA (7th ed.) Citation

SENTHILPARI, C., SINGH, A., & DIWAKAR, K. (2008). Design of a low-power, high performance, 8×8bit multiplier using a Shannon-based adder cell. ELSEVIER SCI LTD.

Chicago Style (17th ed.) Citation

SENTHILPARI, C., A. SINGH, and K. DIWAKAR. Design of a Low-power, High Performance, 8×8bit Multiplier Using a Shannon-based Adder Cell. ELSEVIER SCI LTD, 2008.

MLA (9th ed.) Citation

SENTHILPARI, C., et al. Design of a Low-power, High Performance, 8×8bit Multiplier Using a Shannon-based Adder Cell. ELSEVIER SCI LTD, 2008.