A fast-lock delay-locked loop architecture with improved precharged PFD
In this paper, a dual charge pump architecture for fast-lock delay-locked loop (DLL) is proposed and analyzed. The proposed fast lock DLL uses only one phase frequency detector (PFD) to perform dual path tuning and a lock control circuit to control the switching between the two path. An improved PFD...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
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SPRINGER
2008
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| Online Access: | http://shdl.mmu.edu.my/2738/ http://shdl.mmu.edu.my/2738/1/779.pdf |
| _version_ | 1848790136535384064 |
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| author | Lip-Kai, Soh Sulaiman, Mohd-Shahiman Yusoff, Zubaida |
| author_facet | Lip-Kai, Soh Sulaiman, Mohd-Shahiman Yusoff, Zubaida |
| author_sort | Lip-Kai, Soh |
| building | MMU Institutional Repository |
| collection | Online Access |
| description | In this paper, a dual charge pump architecture for fast-lock delay-locked loop (DLL) is proposed and analyzed. The proposed fast lock DLL uses only one phase frequency detector (PFD) to perform dual path tuning and a lock control circuit to control the switching between the two path. An improved PFD is proposed to reduce the output jitter by reducing the one-shot pulse produced when the reference signal and feedback signal is in phase. The proposed DLL circuit is designed based on the Silterra 0.18-mu m 1P6M CMOS process with a 1.8-V supply voltage. The active area of the proposed DLL circuit is 327.46 x 116.16 mu m. An experimental chip was implemented and measured. The measurement results show that the proposed DLL has fast locking properties. |
| first_indexed | 2025-11-14T18:07:49Z |
| format | Article |
| id | mmu-2738 |
| institution | Multimedia University |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-14T18:07:49Z |
| publishDate | 2008 |
| publisher | SPRINGER |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | mmu-27382014-02-13T07:44:51Z http://shdl.mmu.edu.my/2738/ A fast-lock delay-locked loop architecture with improved precharged PFD Lip-Kai, Soh Sulaiman, Mohd-Shahiman Yusoff, Zubaida T Technology (General) QA75.5-76.95 Electronic computers. Computer science In this paper, a dual charge pump architecture for fast-lock delay-locked loop (DLL) is proposed and analyzed. The proposed fast lock DLL uses only one phase frequency detector (PFD) to perform dual path tuning and a lock control circuit to control the switching between the two path. An improved PFD is proposed to reduce the output jitter by reducing the one-shot pulse produced when the reference signal and feedback signal is in phase. The proposed DLL circuit is designed based on the Silterra 0.18-mu m 1P6M CMOS process with a 1.8-V supply voltage. The active area of the proposed DLL circuit is 327.46 x 116.16 mu m. An experimental chip was implemented and measured. The measurement results show that the proposed DLL has fast locking properties. SPRINGER 2008-05 Article NonPeerReviewed text en http://shdl.mmu.edu.my/2738/1/779.pdf Lip-Kai, Soh and Sulaiman, Mohd-Shahiman and Yusoff, Zubaida (2008) A fast-lock delay-locked loop architecture with improved precharged PFD. Analog Integrated Circuits and Signal Processing, 55 (2). pp. 149-154. ISSN 0925-1030 http://dx.doi.org/10.1007/s10470-008-9131-7 doi:10.1007/s10470-008-9131-7 doi:10.1007/s10470-008-9131-7 |
| spellingShingle | T Technology (General) QA75.5-76.95 Electronic computers. Computer science Lip-Kai, Soh Sulaiman, Mohd-Shahiman Yusoff, Zubaida A fast-lock delay-locked loop architecture with improved precharged PFD |
| title | A fast-lock delay-locked loop architecture with improved precharged PFD |
| title_full | A fast-lock delay-locked loop architecture with improved precharged PFD |
| title_fullStr | A fast-lock delay-locked loop architecture with improved precharged PFD |
| title_full_unstemmed | A fast-lock delay-locked loop architecture with improved precharged PFD |
| title_short | A fast-lock delay-locked loop architecture with improved precharged PFD |
| title_sort | fast-lock delay-locked loop architecture with improved precharged pfd |
| topic | T Technology (General) QA75.5-76.95 Electronic computers. Computer science |
| url | http://shdl.mmu.edu.my/2738/ http://shdl.mmu.edu.my/2738/ http://shdl.mmu.edu.my/2738/ http://shdl.mmu.edu.my/2738/1/779.pdf |