High-level language and compiler for reconfigurable computing
This paper presents a high-level, algorithmic, single-assignment programming language and its tailor-made optimizing compiler. The compiler is able to generate a synthesizable hardware description language for reconfigurable systems based on input instruction set. Simulated annealing and force-direc...
| Main Authors: | , |
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| Format: | Article |
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2004
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| Online Access: | http://shdl.mmu.edu.my/2520/ |
| _version_ | 1848790077831905280 |
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| author | Hiew,, FS Koay, , KH |
| author_facet | Hiew,, FS Koay, , KH |
| author_sort | Hiew,, FS |
| building | MMU Institutional Repository |
| collection | Online Access |
| description | This paper presents a high-level, algorithmic, single-assignment programming language and its tailor-made optimizing compiler. The compiler is able to generate a synthesizable hardware description language for reconfigurable systems based on input instruction set. Simulated annealing and force-directed scheduling approaches were employed in this compiler for design speed and resource optimizations. The tasks of the designed compiler include control flow graph transformation, component selection, component scheduling, and VHDL transformation. Language features are introduced and the structure of the compiler is discussed. |
| first_indexed | 2025-11-14T18:06:53Z |
| format | Article |
| id | mmu-2520 |
| institution | Multimedia University |
| institution_category | Local University |
| last_indexed | 2025-11-14T18:06:53Z |
| publishDate | 2004 |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | mmu-25202011-08-22T06:36:28Z http://shdl.mmu.edu.my/2520/ High-level language and compiler for reconfigurable computing Hiew,, FS Koay, , KH QA75.5-76.95 Electronic computers. Computer science This paper presents a high-level, algorithmic, single-assignment programming language and its tailor-made optimizing compiler. The compiler is able to generate a synthesizable hardware description language for reconfigurable systems based on input instruction set. Simulated annealing and force-directed scheduling approaches were employed in this compiler for design speed and resource optimizations. The tasks of the designed compiler include control flow graph transformation, component selection, component scheduling, and VHDL transformation. Language features are introduced and the structure of the compiler is discussed. 2004 Article NonPeerReviewed Hiew,, FS and Koay, , KH (2004) High-level language and compiler for reconfigurable computing. COMPUTATIONAL AND INFORMATION SCIENCE, PROCEEDINGS, 3314 . pp. 200-206. ISSN 0302-9743 |
| spellingShingle | QA75.5-76.95 Electronic computers. Computer science Hiew,, FS Koay, , KH High-level language and compiler for reconfigurable computing |
| title | High-level language and compiler for reconfigurable computing |
| title_full | High-level language and compiler for reconfigurable computing |
| title_fullStr | High-level language and compiler for reconfigurable computing |
| title_full_unstemmed | High-level language and compiler for reconfigurable computing |
| title_short | High-level language and compiler for reconfigurable computing |
| title_sort | high-level language and compiler for reconfigurable computing |
| topic | QA75.5-76.95 Electronic computers. Computer science |
| url | http://shdl.mmu.edu.my/2520/ |