| Summary: | This paper presents a high-level, algorithmic, single-assignment programming language and its tailor-made optimizing compiler. The compiler is able to generate a synthesizable hardware description language for reconfigurable systems based on input instruction set. Simulated annealing and force-directed scheduling approaches were employed in this compiler for design speed and resource optimizations. The tasks of the designed compiler include control flow graph transformation, component selection, component scheduling, and VHDL transformation. Language features are introduced and the structure of the compiler is discussed.
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