A 160-mhz 45-mW asynchronous dual-port 1-mb CMOS SRAM - Soon-Hwei, , Tan; Sulaiman, , Mohd S.; Poh-Yee, , Loh (2005)
A 160-Mhz 45-mW asynchronous dual-port 1-Mb CMOS SRAM is described. A minimum read access time of 4.26ns is achieved, with an active power figure of 31 mW, data retention capability at 0.1 V VDD across all skews with varied temperature, and yet consume a standby power of only 80nW. Simulation results show that the circuit functions properly over a wide range of Process, Voltage & Temperature (PVT) corners. SRAM was custom designed using TSMC CMOS 0.25 mu m 1P5M Salicide process with a total die size of approximately 115mm(2).