A 160-mhz 45-mW asynchronous dual-port 1-mb CMOS SRAM
A 160-Mhz 45-mW asynchronous dual-port 1-Mb CMOS SRAM is described. A minimum read access time of 4.26ns is achieved, with an active power figure of 31 mW, data retention capability at 0.1 V VDD across all skews with varied temperature, and yet consume a standby power of only 80nW. Simulation result...
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| Format: | Article |
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2005
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| Online Access: | http://shdl.mmu.edu.my/2406/ |
| _version_ | 1848790047234457600 |
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| author | Soon-Hwei, , Tan Sulaiman, , Mohd S. Poh-Yee, , Loh |
| author_facet | Soon-Hwei, , Tan Sulaiman, , Mohd S. Poh-Yee, , Loh |
| author_sort | Soon-Hwei, , Tan |
| building | MMU Institutional Repository |
| collection | Online Access |
| description | A 160-Mhz 45-mW asynchronous dual-port 1-Mb CMOS SRAM is described. A minimum read access time of 4.26ns is achieved, with an active power figure of 31 mW, data retention capability at 0.1 V VDD across all skews with varied temperature, and yet consume a standby power of only 80nW. Simulation results show that the circuit functions properly over a wide range of Process, Voltage & Temperature (PVT) corners. SRAM was custom designed using TSMC CMOS 0.25 mu m 1P5M Salicide process with a total die size of approximately 115mm(2). |
| first_indexed | 2025-11-14T18:06:24Z |
| format | Article |
| id | mmu-2406 |
| institution | Multimedia University |
| institution_category | Local University |
| last_indexed | 2025-11-14T18:06:24Z |
| publishDate | 2005 |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | mmu-24062011-08-22T03:02:32Z http://shdl.mmu.edu.my/2406/ A 160-mhz 45-mW asynchronous dual-port 1-mb CMOS SRAM Soon-Hwei, , Tan Sulaiman, , Mohd S. Poh-Yee, , Loh TA Engineering (General). Civil engineering (General) A 160-Mhz 45-mW asynchronous dual-port 1-Mb CMOS SRAM is described. A minimum read access time of 4.26ns is achieved, with an active power figure of 31 mW, data retention capability at 0.1 V VDD across all skews with varied temperature, and yet consume a standby power of only 80nW. Simulation results show that the circuit functions properly over a wide range of Process, Voltage & Temperature (PVT) corners. SRAM was custom designed using TSMC CMOS 0.25 mu m 1P5M Salicide process with a total die size of approximately 115mm(2). 2005 Article NonPeerReviewed Soon-Hwei, , Tan and Sulaiman, , Mohd S. and Poh-Yee, , Loh (2005) A 160-mhz 45-mW asynchronous dual-port 1-mb CMOS SRAM. 2005 IEEE CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS, PROCEEDINGS. pp. 351-354. |
| spellingShingle | TA Engineering (General). Civil engineering (General) Soon-Hwei, , Tan Sulaiman, , Mohd S. Poh-Yee, , Loh A 160-mhz 45-mW asynchronous dual-port 1-mb CMOS SRAM |
| title | A 160-mhz 45-mW asynchronous dual-port 1-mb CMOS SRAM |
| title_full | A 160-mhz 45-mW asynchronous dual-port 1-mb CMOS SRAM |
| title_fullStr | A 160-mhz 45-mW asynchronous dual-port 1-mb CMOS SRAM |
| title_full_unstemmed | A 160-mhz 45-mW asynchronous dual-port 1-mb CMOS SRAM |
| title_short | A 160-mhz 45-mW asynchronous dual-port 1-mb CMOS SRAM |
| title_sort | 160-mhz 45-mw asynchronous dual-port 1-mb cmos sram |
| topic | TA Engineering (General). Civil engineering (General) |
| url | http://shdl.mmu.edu.my/2406/ |