A low-power high-speed 1-mb CMOS SRAM
An asynchronous dual-port 1-Mb CMOS SRAM is described. The SRAM can operate at a maximum frequency of 220MHz in dual-port mode and dissipates a minimum active power of 31mW and consumes a minimum standby power of 80nW. Simulation results show that the circuit functions properly over a wide range of...
| Main Authors: | , , |
|---|---|
| Format: | Article |
| Published: |
2006
|
| Subjects: | |
| Online Access: | http://shdl.mmu.edu.my/2081/ |
| _version_ | 1848789959295631360 |
|---|---|
| author | Tan, , SH Loh, , PY Sulaiman, , MS |
| author_facet | Tan, , SH Loh, , PY Sulaiman, , MS |
| author_sort | Tan, , SH |
| building | MMU Institutional Repository |
| collection | Online Access |
| description | An asynchronous dual-port 1-Mb CMOS SRAM is described. The SRAM can operate at a maximum frequency of 220MHz in dual-port mode and dissipates a minimum active power of 31mW and consumes a minimum standby power of 80nW. Simulation results show that the circuit functions properly over a wide range of Process, Voltage & Temperature (PVT) corners. SRAM was custom designed using TSMC CMOS 0.25 mu m 1P5M Salicide process and occupies a Silicon area of approximately 115mm(2) (11.5mm x 10mm). |
| first_indexed | 2025-11-14T18:05:00Z |
| format | Article |
| id | mmu-2081 |
| institution | Multimedia University |
| institution_category | Local University |
| last_indexed | 2025-11-14T18:05:00Z |
| publishDate | 2006 |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | mmu-20812011-09-23T02:42:53Z http://shdl.mmu.edu.my/2081/ A low-power high-speed 1-mb CMOS SRAM Tan, , SH Loh, , PY Sulaiman, , MS TA Engineering (General). Civil engineering (General) An asynchronous dual-port 1-Mb CMOS SRAM is described. The SRAM can operate at a maximum frequency of 220MHz in dual-port mode and dissipates a minimum active power of 31mW and consumes a minimum standby power of 80nW. Simulation results show that the circuit functions properly over a wide range of Process, Voltage & Temperature (PVT) corners. SRAM was custom designed using TSMC CMOS 0.25 mu m 1P5M Salicide process and occupies a Silicon area of approximately 115mm(2) (11.5mm x 10mm). 2006 Article NonPeerReviewed Tan, , SH and Loh, , PY and Sulaiman, , MS (2006) A low-power high-speed 1-mb CMOS SRAM. DELTA 2006: THIRD IEEE INTERNATIONAL WORKSHOP ON ELECTRONIC DESIGN, TEST AND APPLICATIONS. pp. 281-286. |
| spellingShingle | TA Engineering (General). Civil engineering (General) Tan, , SH Loh, , PY Sulaiman, , MS A low-power high-speed 1-mb CMOS SRAM |
| title | A low-power high-speed 1-mb CMOS SRAM |
| title_full | A low-power high-speed 1-mb CMOS SRAM |
| title_fullStr | A low-power high-speed 1-mb CMOS SRAM |
| title_full_unstemmed | A low-power high-speed 1-mb CMOS SRAM |
| title_short | A low-power high-speed 1-mb CMOS SRAM |
| title_sort | low-power high-speed 1-mb cmos sram |
| topic | TA Engineering (General). Civil engineering (General) |
| url | http://shdl.mmu.edu.my/2081/ |