Impact of technology on PLL power and frequency
Purpose - This paper presents a prediction on the impact of technology scaling on phase-locked loop (PLL) performance behaviour. Power and maximum operating frequency of an Analogue PLL and a Type II phase-frequency detector (PFD)-based PLL from which the behaviours of other PLLs derived from the tw...
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| Format: | Article |
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2006
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| Online Access: | http://shdl.mmu.edu.my/2072/ |
| _version_ | 1848789956709842944 |
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| author | Sulaiman, Mohd-Shahiman |
| author_facet | Sulaiman, Mohd-Shahiman |
| author_sort | Sulaiman, Mohd-Shahiman |
| building | MMU Institutional Repository |
| collection | Online Access |
| description | Purpose - This paper presents a prediction on the impact of technology scaling on phase-locked loop (PLL) performance behaviour. Power and maximum operating frequency of an Analogue PLL and a Type II phase-frequency detector (PFD)-based PLL from which the behaviours of other PLLs derived from the two architectures can be estimated, are analysed and their future behaviours as a function of technology are predicted.
Design/methodology/approach - Analogue models were developed and Mentor Graphics VHDL-AMS mixed-signal simulations were performed on the two PLL architectures. Behavioural power and frequency equations as a function of technology were derived based on thorough data and graphical analyses.
Findings - A prediction of PLL frequency and power dissipation as a function of technology for two main PLL architectures.
Research limitations/implications - The parameters in each equation derived should include other contributing factors as well as other design approaches such as multi-VDD, multi-Vth, etc. future work should also include prediction of jitter and phase noise for the two main PLL topologies.
Originality/value - This paper is of high significance in PLL design. The predicted equations could be used to reduce a major portion of a PLL designers' design time when choosing a PLL topology, and help them predict the impact of technology on the performance of the chosen architecture. |
| first_indexed | 2025-11-14T18:04:58Z |
| format | Article |
| id | mmu-2072 |
| institution | Multimedia University |
| institution_category | Local University |
| last_indexed | 2025-11-14T18:04:58Z |
| publishDate | 2006 |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | mmu-20722011-08-10T07:19:43Z http://shdl.mmu.edu.my/2072/ Impact of technology on PLL power and frequency Sulaiman, Mohd-Shahiman TA Engineering (General). Civil engineering (General) Purpose - This paper presents a prediction on the impact of technology scaling on phase-locked loop (PLL) performance behaviour. Power and maximum operating frequency of an Analogue PLL and a Type II phase-frequency detector (PFD)-based PLL from which the behaviours of other PLLs derived from the two architectures can be estimated, are analysed and their future behaviours as a function of technology are predicted. Design/methodology/approach - Analogue models were developed and Mentor Graphics VHDL-AMS mixed-signal simulations were performed on the two PLL architectures. Behavioural power and frequency equations as a function of technology were derived based on thorough data and graphical analyses. Findings - A prediction of PLL frequency and power dissipation as a function of technology for two main PLL architectures. Research limitations/implications - The parameters in each equation derived should include other contributing factors as well as other design approaches such as multi-VDD, multi-Vth, etc. future work should also include prediction of jitter and phase noise for the two main PLL topologies. Originality/value - This paper is of high significance in PLL design. The predicted equations could be used to reduce a major portion of a PLL designers' design time when choosing a PLL topology, and help them predict the impact of technology on the performance of the chosen architecture. 2006 Article NonPeerReviewed Sulaiman, Mohd-Shahiman (2006) Impact of technology on PLL power and frequency. Microelectronics International, 23 (3). pp. 49-54. ISSN 1356-5362 http://dx.doi.org/10.1108/13565360610680767 doi:10.1108/13565360610680767 doi:10.1108/13565360610680767 |
| spellingShingle | TA Engineering (General). Civil engineering (General) Sulaiman, Mohd-Shahiman Impact of technology on PLL power and frequency |
| title | Impact of technology on PLL power and frequency |
| title_full | Impact of technology on PLL power and frequency |
| title_fullStr | Impact of technology on PLL power and frequency |
| title_full_unstemmed | Impact of technology on PLL power and frequency |
| title_short | Impact of technology on PLL power and frequency |
| title_sort | impact of technology on pll power and frequency |
| topic | TA Engineering (General). Civil engineering (General) |
| url | http://shdl.mmu.edu.my/2072/ http://shdl.mmu.edu.my/2072/ http://shdl.mmu.edu.my/2072/ |