| Summary: | Purpose - This paper presents a prediction on the impact of technology scaling on phase-locked loop (PLL) performance behaviour. Power and maximum operating frequency of an Analogue PLL and a Type II phase-frequency detector (PFD)-based PLL from which the behaviours of other PLLs derived from the two architectures can be estimated, are analysed and their future behaviours as a function of technology are predicted.
Design/methodology/approach - Analogue models were developed and Mentor Graphics VHDL-AMS mixed-signal simulations were performed on the two PLL architectures. Behavioural power and frequency equations as a function of technology were derived based on thorough data and graphical analyses.
Findings - A prediction of PLL frequency and power dissipation as a function of technology for two main PLL architectures.
Research limitations/implications - The parameters in each equation derived should include other contributing factors as well as other design approaches such as multi-VDD, multi-Vth, etc. future work should also include prediction of jitter and phase noise for the two main PLL topologies.
Originality/value - This paper is of high significance in PLL design. The predicted equations could be used to reduce a major portion of a PLL designers' design time when choosing a PLL topology, and help them predict the impact of technology on the performance of the chosen architecture.
|
|---|