Design of 32-Bit Arithmetic Logic Unit Using Shannon Theorem Based Adder Approach

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Design of 32-Bit Arithmetic Logic Unit Using Shannon Theorem Based Adder Approach

This thesis proposes two new techniques for the design of full adder circuits namely, Mixed-Shannon and Shannon circuits. The Mixed-Shannon adder cell is developed using the MCIT for the sum operation and the Shannon based technique for the carry. In the second technique approach, the full adder cir...

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Bibliographic Details
Main Author:	C., Senthilpari
Format:	Thesis
Published:	2009
Subjects:	TK7800-8360 Electronics
Online Access:	http://shdl.mmu.edu.my/1786/

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