Fast-Lock Low -Jitter Delay Locked Loop

In this thesis, an improved phase frequency detector (PFD) and dual charge pump architecture for fast-lock low -jitter delay-locked loop (DLL) is proposed and analyzed.

Bibliographic Details
Main Author: Soh, Lip Kai
Format: Thesis
Published: 2007
Subjects:
Online Access:http://shdl.mmu.edu.my/1224/
_version_ 1848789727952502784
author Soh, Lip Kai
author_facet Soh, Lip Kai
author_sort Soh, Lip Kai
building MMU Institutional Repository
collection Online Access
description In this thesis, an improved phase frequency detector (PFD) and dual charge pump architecture for fast-lock low -jitter delay-locked loop (DLL) is proposed and analyzed.
first_indexed 2025-11-14T18:01:19Z
format Thesis
id mmu-1224
institution Multimedia University
institution_category Local University
last_indexed 2025-11-14T18:01:19Z
publishDate 2007
recordtype eprints
repository_type Digital Repository
spelling mmu-12242010-08-19T05:56:49Z http://shdl.mmu.edu.my/1224/ Fast-Lock Low -Jitter Delay Locked Loop Soh, Lip Kai TK7800-8360 Electronics In this thesis, an improved phase frequency detector (PFD) and dual charge pump architecture for fast-lock low -jitter delay-locked loop (DLL) is proposed and analyzed. 2007-12 Thesis NonPeerReviewed Soh, Lip Kai (2007) Fast-Lock Low -Jitter Delay Locked Loop. Masters thesis, Multimedia University. http://myto.perpun.net.my/metoalogin/logina.php
spellingShingle TK7800-8360 Electronics
Soh, Lip Kai
Fast-Lock Low -Jitter Delay Locked Loop
title Fast-Lock Low -Jitter Delay Locked Loop
title_full Fast-Lock Low -Jitter Delay Locked Loop
title_fullStr Fast-Lock Low -Jitter Delay Locked Loop
title_full_unstemmed Fast-Lock Low -Jitter Delay Locked Loop
title_short Fast-Lock Low -Jitter Delay Locked Loop
title_sort fast-lock low -jitter delay locked loop
topic TK7800-8360 Electronics
url http://shdl.mmu.edu.my/1224/
http://shdl.mmu.edu.my/1224/