Design Allocation And Scheduling Hardware Compiler For Digital Data Processing In FPGA

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Design Allocation And Scheduling Hardware Compiler For Digital Data Processing In FPGA

In this project, a high-level language and its automated compiler are proposed to automatically transform the language into a synthesizable RTL-level VHDL design. The proposed language, named as Simple Algorithmic Language for Hardware Design (SALH), is simple to use and featured single-assignment,...

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Bibliographic Details
Main Author:	Hiew, Fu San
Format:	Thesis
Published:	2006
Subjects:	TK7800-8360 Electronics
Online Access:	http://shdl.mmu.edu.my/1207/

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