Design Allocation And Scheduling Hardware Compiler For Digital Data Processing In FPGA
In this project, a high-level language and its automated compiler are proposed to automatically transform the language into a synthesizable RTL-level VHDL design. The proposed language, named as Simple Algorithmic Language for Hardware Design (SALH), is simple to use and featured single-assignment,...
| Main Author: | |
|---|---|
| Format: | Thesis |
| Published: |
2006
|
| Subjects: | |
| Online Access: | http://shdl.mmu.edu.my/1207/ |
| _version_ | 1848789723324088320 |
|---|---|
| author | Hiew, Fu San |
| author_facet | Hiew, Fu San |
| author_sort | Hiew, Fu San |
| building | MMU Institutional Repository |
| collection | Online Access |
| description | In this project, a high-level language and its automated compiler are proposed to automatically transform the language into a synthesizable RTL-level VHDL design. The proposed language, named as Simple Algorithmic Language for Hardware Design (SALH), is simple to use and featured single-assignment, in which it can reduce the coding lengthiness. |
| first_indexed | 2025-11-14T18:01:15Z |
| format | Thesis |
| id | mmu-1207 |
| institution | Multimedia University |
| institution_category | Local University |
| last_indexed | 2025-11-14T18:01:15Z |
| publishDate | 2006 |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | mmu-12072010-08-19T08:21:34Z http://shdl.mmu.edu.my/1207/ Design Allocation And Scheduling Hardware Compiler For Digital Data Processing In FPGA Hiew, Fu San TK7800-8360 Electronics In this project, a high-level language and its automated compiler are proposed to automatically transform the language into a synthesizable RTL-level VHDL design. The proposed language, named as Simple Algorithmic Language for Hardware Design (SALH), is simple to use and featured single-assignment, in which it can reduce the coding lengthiness. 2006-10 Thesis NonPeerReviewed Hiew, Fu San (2006) Design Allocation And Scheduling Hardware Compiler For Digital Data Processing In FPGA. Masters thesis, Multimedia University. http://myto.perpun.net.my/metoalogin/logina.php |
| spellingShingle | TK7800-8360 Electronics Hiew, Fu San Design Allocation And Scheduling Hardware Compiler For Digital Data Processing In FPGA |
| title | Design Allocation And Scheduling Hardware Compiler For Digital Data Processing In FPGA |
| title_full | Design Allocation And Scheduling Hardware Compiler For Digital Data Processing In FPGA |
| title_fullStr | Design Allocation And Scheduling Hardware Compiler For Digital Data Processing In FPGA |
| title_full_unstemmed | Design Allocation And Scheduling Hardware Compiler For Digital Data Processing In FPGA |
| title_short | Design Allocation And Scheduling Hardware Compiler For Digital Data Processing In FPGA |
| title_sort | design allocation and scheduling hardware compiler for digital data processing in fpga |
| topic | TK7800-8360 Electronics |
| url | http://shdl.mmu.edu.my/1207/ http://shdl.mmu.edu.my/1207/ |