High-Performance CMOS Clock And Data Recovery Circuit - Tan, Kok Siang (2006)
In this dissertation, the design of a 5Gb/s CDR circuit in Taiwan Semiconductor Manufacturing Corporation (TSMC) 0.18 -1.8V standard CMOS process based on a linear half-rate linear architecture is presented. Half-rate architecture allows a voltage controlled oscillator (VCO) to run at one-half of its input data rate by utilizing both rising and falling edges of VCO output to sample jittery non-return zero (NRZ) data. Having a VCO running at one-half of data rate significantly reduces total jitter and power consumption.