Inter-Processor Communication Performance of a Hierarchical Torus Network under Bit-Flip Traffic Patterns

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Inter-Processor Communication Performance of a Hierarchical Torus Network under Bit-Flip Traffic Patterns

In this paper, we present a deadlock-free routing algorithm for the hierarchical torus network (HTN) using 2 virtual channels - 2 being the minimum number for dimension order routing - and evaluate the network's inter-processor communication performance under the bit-flip traffic pattern using...

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Bibliographic Details
Main Authors:	Rahman, M.M. Hafizur, Ghosh, Manas, Horiguchi, Susumu
Format:	Proceeding Paper
Language:	English
Published:	2006
Subjects:	TK Electrical engineering. Electronics Nuclear engineering
Online Access:	http://irep.iium.edu.my/8227/ http://irep.iium.edu.my/8227/1/ICECE_2006.pdf

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