Hardware prototyping of an efficient encryption engine
An approach to develop the FPGA of a flexible key RSA encryption engine that can be used as a standard device in the secured communication system is presented. The VHDL modeling of this RSA encryption engine has the unique characteristics of supporting multiple key sizes, thus can be fitted into the...
| Main Authors: | , , |
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| Format: | Book Chapter |
| Language: | English |
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IIUM Press
2009
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| Subjects: | |
| Online Access: | http://irep.iium.edu.my/7107/ http://irep.iium.edu.my/7107/1/Hardware_Prototyping_of_an_Efficient_Encryption_Engine.pdf |
| _version_ | 1848776788070629376 |
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| author | Ibrahimy, Muhammad Ibn Reaz, Mamun Bin Ibne Hussain, S. |
| author_facet | Ibrahimy, Muhammad Ibn Reaz, Mamun Bin Ibne Hussain, S. |
| author_sort | Ibrahimy, Muhammad Ibn |
| building | IIUM Repository |
| collection | Online Access |
| description | An approach to develop the FPGA of a flexible key RSA encryption engine that can be used as a standard device in the secured communication system is presented. The VHDL modeling of this RSA encryption engine has the unique characteristics of supporting multiple key sizes, thus can be fitted into the systems that require different levels of security. A simple nested loop addition and subtraction have been used to implement the RSA operation. This has made the processing time faster and used comparatively smaller amount of space in the FPGA. The hardware design is targeted on Althera STRATIX II device and determined that the flexible key RSA encryption engine can be best suited in the device named EP2S30F484C3. The RSA encryption implementation has made use of 13,779 units of logic elements and achieved a clock frequency of 17.77HHz. It has been verified that this RSA encryption engine can perform 32-bit, 256-bit and 1024-bit encryption operation in less than 41.585US, 531.515US and 790.61US respectively. |
| first_indexed | 2025-11-14T14:35:39Z |
| format | Book Chapter |
| id | iium-7107 |
| institution | International Islamic University Malaysia |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-14T14:35:39Z |
| publishDate | 2009 |
| publisher | IIUM Press |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | iium-71072011-11-23T01:34:44Z http://irep.iium.edu.my/7107/ Hardware prototyping of an efficient encryption engine Ibrahimy, Muhammad Ibn Reaz, Mamun Bin Ibne Hussain, S. TA Engineering (General). Civil engineering (General) An approach to develop the FPGA of a flexible key RSA encryption engine that can be used as a standard device in the secured communication system is presented. The VHDL modeling of this RSA encryption engine has the unique characteristics of supporting multiple key sizes, thus can be fitted into the systems that require different levels of security. A simple nested loop addition and subtraction have been used to implement the RSA operation. This has made the processing time faster and used comparatively smaller amount of space in the FPGA. The hardware design is targeted on Althera STRATIX II device and determined that the flexible key RSA encryption engine can be best suited in the device named EP2S30F484C3. The RSA encryption implementation has made use of 13,779 units of logic elements and achieved a clock frequency of 17.77HHz. It has been verified that this RSA encryption engine can perform 32-bit, 256-bit and 1024-bit encryption operation in less than 41.585US, 531.515US and 790.61US respectively. IIUM Press 2009 Book Chapter PeerReviewed application/pdf en http://irep.iium.edu.my/7107/1/Hardware_Prototyping_of_an_Efficient_Encryption_Engine.pdf Ibrahimy, Muhammad Ibn and Reaz, Mamun Bin Ibne and Hussain, S. (2009) Hardware prototyping of an efficient encryption engine. In: Proceedings of the Seminar on Research Findings 2008. IIUM Press, Kuala Lumpur, pp. 421-430. ISBN 9789833855780 http://rms.research.iium.edu.my/bookstore/Products/115-wwwgooglecom.aspx |
| spellingShingle | TA Engineering (General). Civil engineering (General) Ibrahimy, Muhammad Ibn Reaz, Mamun Bin Ibne Hussain, S. Hardware prototyping of an efficient encryption engine |
| title | Hardware prototyping of an efficient encryption engine |
| title_full | Hardware prototyping of an efficient encryption engine |
| title_fullStr | Hardware prototyping of an efficient encryption engine |
| title_full_unstemmed | Hardware prototyping of an efficient encryption engine |
| title_short | Hardware prototyping of an efficient encryption engine |
| title_sort | hardware prototyping of an efficient encryption engine |
| topic | TA Engineering (General). Civil engineering (General) |
| url | http://irep.iium.edu.my/7107/ http://irep.iium.edu.my/7107/ http://irep.iium.edu.my/7107/1/Hardware_Prototyping_of_an_Efficient_Encryption_Engine.pdf |