Design and implementation of a five stage pipelining architecture simulator for RiSC-16 instruction set
In modern computing, multitasking is the most favorable aspect. An un-pipelined instruction cycle (fetch-execute cycle) CPU processes instructions one after another increasing duration at lesser speed in completing tasks. With pipelined computer architecture, unprecedented improvement in size and...
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| Format: | Article |
| Language: | English |
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Indian Society of Education and Environment
2017
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| Online Access: | http://irep.iium.edu.my/56118/ http://irep.iium.edu.my/56118/1/Design%20of%20Pipeline%20published.pdf |
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| author | Olanrewaju, Rashidah Funke Fajingbesi, Fawwaz Eniola Junaid, S. B. Alahudin, Ridzwan Anwar, Farhat pampori, Bisma Rasol |
| author_facet | Olanrewaju, Rashidah Funke Fajingbesi, Fawwaz Eniola Junaid, S. B. Alahudin, Ridzwan Anwar, Farhat pampori, Bisma Rasol |
| author_sort | Olanrewaju, Rashidah Funke |
| building | IIUM Repository |
| collection | Online Access |
| description | In modern computing, multitasking is the most favorable aspect. An un-pipelined instruction cycle (fetch-execute cycle)
CPU processes instructions one after another increasing duration at lesser speed in completing tasks. With pipelined
computer architecture, unprecedented improvement in size and speed are achievable. This work investigates the possibility
of a better improvement to computer architecture through understanding the inner workings of instruction pipelining
in operating system. A design of a 5 stage pipelined architecture simulator for RiSC-16 processors using Visual Basic
programming has been achieved contrary to the common available four stage simulators. The simulator also future two
most common pipeline instruction hazards generally missing in most available simulators. Thus, the designed simulator
becomes an appropriate tool for understanding the concept of pipelining on a step-by-step visualization based instruction cycle
processors hence facilitating a more efficient design in computer architecture. The simulator has been evaluated
based on its closeness to real-time pipelined computer architecture and through execution of all 8 basic RiSC-16 instruction
set with data dependency and control hazard. |
| first_indexed | 2025-11-14T16:41:11Z |
| format | Article |
| id | iium-56118 |
| institution | International Islamic University Malaysia |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-14T16:41:11Z |
| publishDate | 2017 |
| publisher | Indian Society of Education and Environment |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | iium-561182019-11-28T00:56:52Z http://irep.iium.edu.my/56118/ Design and implementation of a five stage pipelining architecture simulator for RiSC-16 instruction set Olanrewaju, Rashidah Funke Fajingbesi, Fawwaz Eniola Junaid, S. B. Alahudin, Ridzwan Anwar, Farhat pampori, Bisma Rasol TK7800 Electronics. Computer engineering. Computer hardware. Photoelectronic devices In modern computing, multitasking is the most favorable aspect. An un-pipelined instruction cycle (fetch-execute cycle) CPU processes instructions one after another increasing duration at lesser speed in completing tasks. With pipelined computer architecture, unprecedented improvement in size and speed are achievable. This work investigates the possibility of a better improvement to computer architecture through understanding the inner workings of instruction pipelining in operating system. A design of a 5 stage pipelined architecture simulator for RiSC-16 processors using Visual Basic programming has been achieved contrary to the common available four stage simulators. The simulator also future two most common pipeline instruction hazards generally missing in most available simulators. Thus, the designed simulator becomes an appropriate tool for understanding the concept of pipelining on a step-by-step visualization based instruction cycle processors hence facilitating a more efficient design in computer architecture. The simulator has been evaluated based on its closeness to real-time pipelined computer architecture and through execution of all 8 basic RiSC-16 instruction set with data dependency and control hazard. Indian Society of Education and Environment 2017-01 Article PeerReviewed application/pdf en http://irep.iium.edu.my/56118/1/Design%20of%20Pipeline%20published.pdf Olanrewaju, Rashidah Funke and Fajingbesi, Fawwaz Eniola and Junaid, S. B. and Alahudin, Ridzwan and Anwar, Farhat and pampori, Bisma Rasol (2017) Design and implementation of a five stage pipelining architecture simulator for RiSC-16 instruction set. Indian Journal of Science and Technology, 10 (3). pp. 1-9. ISSN 0974-6846 E-ISSN 0974-5645 http://www.indjst.org/index.php/indjst/article/view/110622/77994 10.17485/ijst/2017/v10i3/110622 |
| spellingShingle | TK7800 Electronics. Computer engineering. Computer hardware. Photoelectronic devices Olanrewaju, Rashidah Funke Fajingbesi, Fawwaz Eniola Junaid, S. B. Alahudin, Ridzwan Anwar, Farhat pampori, Bisma Rasol Design and implementation of a five stage pipelining architecture simulator for RiSC-16 instruction set |
| title | Design and implementation of a five stage pipelining architecture simulator for RiSC-16 instruction set |
| title_full | Design and implementation of a five stage pipelining architecture simulator for RiSC-16 instruction set |
| title_fullStr | Design and implementation of a five stage pipelining architecture simulator for RiSC-16 instruction set |
| title_full_unstemmed | Design and implementation of a five stage pipelining architecture simulator for RiSC-16 instruction set |
| title_short | Design and implementation of a five stage pipelining architecture simulator for RiSC-16 instruction set |
| title_sort | design and implementation of a five stage pipelining architecture simulator for risc-16 instruction set |
| topic | TK7800 Electronics. Computer engineering. Computer hardware. Photoelectronic devices |
| url | http://irep.iium.edu.my/56118/ http://irep.iium.edu.my/56118/ http://irep.iium.edu.my/56118/ http://irep.iium.edu.my/56118/1/Design%20of%20Pipeline%20published.pdf |