An efficient cache replacement algorithm for minimizing the error rate in L2-STT-MRAM caches

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An efficient cache replacement algorithm for minimizing the error rate in L2-STT-MRAM caches

In the recent times, various challenges are being encountered during SRAM cache design and development which lead to a situation of converting the memory cell technologies into on-chip embedded caches. The current research statistics towards cache designing reveals that Spin Torque Transfer Magneti...

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Bibliographic Details
Main Authors:	Olanrewaju, Rashidah Funke, Asifa Mehraj Baba, Asifa Mehraj, Khan, Burhan Ul Islam, Yaacob, Mashkuri, Azman, Amelia Wong, Mir, Mohammad Shuaib
Format:	Proceeding Paper
Language:	English English
Published:	IEEE 2017
Subjects:	TK7885 Computer engineering
Online Access:	http://irep.iium.edu.my/55972/ http://irep.iium.edu.my/55972/7/55972%20An%20efficient%20cache%20replacement%20algorithm.pdf http://irep.iium.edu.my/55972/8/55972%20An%20efficient%20cache%20replacement%20algorithm%20SCOPUS.pdf

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