SCCN: a cost effective hierarchical interconnection network for network-on-chip - N. M. Ali, Mohammed; Rahman, M.M. Hafizur; Mohd. Nor, Rizal; Tengku Sembok, Tengku Mohd (IJACT Inc., 2016)
The structure of the interconnection networks has a crucial effect on the speed of the multi-core processor systems. Sequential computer systems with single CPU core reached their saturation, and they cannot provide high computing power to meet the new technology requirements. Therefore, many designs of interconnection networks have been proposed seeking for good performance and low cost network. However, still there is no clear winner between all these networks. In this paper, we propose a new hierarchical interconnection network called shifted completely connected network (SCCN); this network is composed of six nodes are connected completely to construct the basic module (BM) of this network. In addition, the basic modules (BMs) of SCCN are connected through global links to build up the higher level networks. The static network performance parameters of SCCN have been evaluated; these parameters include: node degree, diameter, cost, arc connectivity, bisection width, wiring complexity, average distance, packing density, massage traffic density, and finally cost effectiveness factor. SCCN reveals low cost in both cost and cost effectiveness factor parameters. In addition, it reveals small diameter, high packing density, and less massage traffic density comparing to the popular networks 2D-mesh and 2D-torus. In addition, it shows the superiority over these networks in all aspects. Hence, SCCN could be a good choice to replace the conventional networks in building the future generations of the massively parallel computer systems (MPC).