Design consideration for successful delay fault testing in SOC

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Design consideration for successful delay fault testing in SOC

Delay Fault Testing using scan patterns has been increasingly popular in the DFT world. There’s a debate whether at-speed test with scan patterns can actually replace functional at-speed tests. This paper looks at some of the design considerations for making SoC more delay test friendly and re...

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Bibliographic Details
Main Authors:	Dass, Sreedharan Baskara, Hassan Abdalla Hashim, Aisha
Format:	Proceeding Paper
Language:	English
Published:	ICECE Publications 2004
Subjects:	TK Electrical engineering. Electronics Nuclear engineering
Online Access:	http://irep.iium.edu.my/50147/ http://irep.iium.edu.my/50147/4/50147.pdf

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