Encryption in TECB mode: modeling, simulation and synthesis

The growth of the Internet as a vehicle for secure communication has resulted in Data Encryption Standard DES) no longer capable of providing high-level security for data protection. Triple Data Encryption Standard (3DES) is a symmetric block cipher with 192 bits key proposed to further enhance DES...

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Main Author: Ibrahimy, Muhammad Ibn
Format: Proceeding Paper
Language:English
Published: 2007
Subjects:
Online Access:http://irep.iium.edu.my/36640/
http://irep.iium.edu.my/36640/1/B1.pdf
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author Ibrahimy, Muhammad Ibn
author_facet Ibrahimy, Muhammad Ibn
author_sort Ibrahimy, Muhammad Ibn
building IIUM Repository
collection Online Access
description The growth of the Internet as a vehicle for secure communication has resulted in Data Encryption Standard DES) no longer capable of providing high-level security for data protection. Triple Data Encryption Standard (3DES) is a symmetric block cipher with 192 bits key proposed to further enhance DES. Many applications crave for the speed of a hardware encryption implementation while trying to preserve the flexibility and low cost of a software implementation. This project used single core module to implement encryption in Triple DES Electronic Code Book (TECB) mode, which was modeled using hardware description language VHDL. The architecture was mapped in Altera EPF10K100EFC484-1 and EP20K200EFC672-1X for performance investigations and resulted in achieving encryption rate of 102.56 Mbps, area utilization of 2111 logic cells (25%) and a higher maximum operating frequency of 78.59MHz by implementing on the larger FPGA device EP20K200EFC672-1X. It also suggested that 3DES hardware was 2.4 times faster than its software coun-terpart.
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spelling iium-366402014-05-16T07:54:48Z http://irep.iium.edu.my/36640/ Encryption in TECB mode: modeling, simulation and synthesis Ibrahimy, Muhammad Ibn T Technology (General) The growth of the Internet as a vehicle for secure communication has resulted in Data Encryption Standard DES) no longer capable of providing high-level security for data protection. Triple Data Encryption Standard (3DES) is a symmetric block cipher with 192 bits key proposed to further enhance DES. Many applications crave for the speed of a hardware encryption implementation while trying to preserve the flexibility and low cost of a software implementation. This project used single core module to implement encryption in Triple DES Electronic Code Book (TECB) mode, which was modeled using hardware description language VHDL. The architecture was mapped in Altera EPF10K100EFC484-1 and EP20K200EFC672-1X for performance investigations and resulted in achieving encryption rate of 102.56 Mbps, area utilization of 2111 logic cells (25%) and a higher maximum operating frequency of 78.59MHz by implementing on the larger FPGA device EP20K200EFC672-1X. It also suggested that 3DES hardware was 2.4 times faster than its software coun-terpart. 2007 Proceeding Paper NonPeerReviewed application/pdf en http://irep.iium.edu.my/36640/1/B1.pdf Ibrahimy, Muhammad Ibn (2007) Encryption in TECB mode: modeling, simulation and synthesis. In: Asia Simulation Conference, 2007, 10-12 October, 2007, Seoul, Korea. http://www.springer.com/computer/theoretical+computer+science/book/978-3-540-77599-7
spellingShingle T Technology (General)
Ibrahimy, Muhammad Ibn
Encryption in TECB mode: modeling, simulation and synthesis
title Encryption in TECB mode: modeling, simulation and synthesis
title_full Encryption in TECB mode: modeling, simulation and synthesis
title_fullStr Encryption in TECB mode: modeling, simulation and synthesis
title_full_unstemmed Encryption in TECB mode: modeling, simulation and synthesis
title_short Encryption in TECB mode: modeling, simulation and synthesis
title_sort encryption in tecb mode: modeling, simulation and synthesis
topic T Technology (General)
url http://irep.iium.edu.my/36640/
http://irep.iium.edu.my/36640/
http://irep.iium.edu.my/36640/1/B1.pdf