Network-on-chip implementation of hierarchical torus network
The interconnection network plays an important role in the performance and energy consumption of a Network-on-Chip (NoC) system. In this paper, we implement the NoC implementation of hierarchical torus network. The Hierarchical Torus Network (HTN) is a hierarchical interconnection network consisti...
| Main Authors: | , , |
|---|---|
| Format: | Proceeding Paper |
| Language: | English English |
| Published: |
2013
|
| Subjects: | |
| Online Access: | http://irep.iium.edu.my/31743/ http://irep.iium.edu.my/31743/1/ICSECS_2013_HTN_24_pub.pdf http://irep.iium.edu.my/31743/4/ICSECS_2013.jpg |
| _version_ | 1848780446343626752 |
|---|---|
| author | Rahman, M.M. Hafizur Ray, Sajib Md. , Rabiul Awal |
| author_facet | Rahman, M.M. Hafizur Ray, Sajib Md. , Rabiul Awal |
| author_sort | Rahman, M.M. Hafizur |
| building | IIUM Repository |
| collection | Online Access |
| description | The interconnection network plays an important role in the
performance and energy consumption of a Network-on-Chip (NoC) system. In this paper, we implement the NoC implementation of hierarchical torus network. The Hierarchical Torus Network (HTN) is a hierarchical
interconnection network consisting of multiple BM that is hierarchically interconnected for higher-level networks. The number of layers needed for routing the links in HTN level-2 is shown to be bounded at 8, which is feasible to be implemented with current and future VLSI technologies.
With the innovative hierarchical structure, HTN possesses the following features: hierarchical structure, smaller diameter and average distance, embedded mesh/torus topology, a constant node degree of 8. These features make HTN a promising solution for the interconnection network of NoC designs satisfying the requirements for scalability, energy efficiency, customizable, and fault-tolerance. |
| first_indexed | 2025-11-14T15:33:48Z |
| format | Proceeding Paper |
| id | iium-31743 |
| institution | International Islamic University Malaysia |
| institution_category | Local University |
| language | English English |
| last_indexed | 2025-11-14T15:33:48Z |
| publishDate | 2013 |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | iium-317432013-09-24T07:40:37Z http://irep.iium.edu.my/31743/ Network-on-chip implementation of hierarchical torus network Rahman, M.M. Hafizur Ray, Sajib Md. , Rabiul Awal TK Electrical engineering. Electronics Nuclear engineering The interconnection network plays an important role in the performance and energy consumption of a Network-on-Chip (NoC) system. In this paper, we implement the NoC implementation of hierarchical torus network. The Hierarchical Torus Network (HTN) is a hierarchical interconnection network consisting of multiple BM that is hierarchically interconnected for higher-level networks. The number of layers needed for routing the links in HTN level-2 is shown to be bounded at 8, which is feasible to be implemented with current and future VLSI technologies. With the innovative hierarchical structure, HTN possesses the following features: hierarchical structure, smaller diameter and average distance, embedded mesh/torus topology, a constant node degree of 8. These features make HTN a promising solution for the interconnection network of NoC designs satisfying the requirements for scalability, energy efficiency, customizable, and fault-tolerance. 2013 Proceeding Paper PeerReviewed application/pdf en http://irep.iium.edu.my/31743/1/ICSECS_2013_HTN_24_pub.pdf application/pdf en http://irep.iium.edu.my/31743/4/ICSECS_2013.jpg Rahman, M.M. Hafizur and Ray, Sajib and Md. , Rabiul Awal (2013) Network-on-chip implementation of hierarchical torus network. In: 3rd International Conference on Software Engineering and Computer Systems (ICSECS - 2013), 20 - 22 August 2013, Kuantan, Pahang. |
| spellingShingle | TK Electrical engineering. Electronics Nuclear engineering Rahman, M.M. Hafizur Ray, Sajib Md. , Rabiul Awal Network-on-chip implementation of hierarchical torus network |
| title | Network-on-chip implementation of hierarchical torus network |
| title_full | Network-on-chip implementation of hierarchical torus network |
| title_fullStr | Network-on-chip implementation of hierarchical torus network |
| title_full_unstemmed | Network-on-chip implementation of hierarchical torus network |
| title_short | Network-on-chip implementation of hierarchical torus network |
| title_sort | network-on-chip implementation of hierarchical torus network |
| topic | TK Electrical engineering. Electronics Nuclear engineering |
| url | http://irep.iium.edu.my/31743/ http://irep.iium.edu.my/31743/1/ICSECS_2013_HTN_24_pub.pdf http://irep.iium.edu.my/31743/4/ICSECS_2013.jpg |