Design of a multiple valued logic analog to digital converter using 0.13μm CMOS process

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Design of a multiple valued logic analog to digital converter using 0.13μm CMOS process

The interconnect and increasing chip density is still poses major threats to the continued development of large scale binary integrated systems and implementation in VLSI using traditional binary logic system. The design and simulation of a Multiple Valued Logic (MVL) Analog-to-Digital Converter (...

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Bibliographic Details
Main Authors:	Farhana, Soheli, Alam, A. H. M. Zahirul, Khan, Sheroz
Format:	Article
Language:	English
Published:	Academic Information Press 2012
Subjects:	TK Electrical engineering. Electronics Nuclear engineering
Online Access:	http://irep.iium.edu.my/24248/ http://irep.iium.edu.my/24248/1/Journal_SSDR.pdf

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