Design of a multiple valued logic analog to digital converter using 0.13μm CMOS process
The interconnect and increasing chip density is still poses major threats to the continued development of large scale binary integrated systems and implementation in VLSI using traditional binary logic system. The design and simulation of a Multiple Valued Logic (MVL) Analog-to-Digital Converter (...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
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Academic Information Press
2012
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| Online Access: | http://irep.iium.edu.my/24248/ http://irep.iium.edu.my/24248/1/Journal_SSDR.pdf |
| _version_ | 1848779272016101376 |
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| author | Farhana, Soheli Alam, A. H. M. Zahirul Khan, Sheroz |
| author_facet | Farhana, Soheli Alam, A. H. M. Zahirul Khan, Sheroz |
| author_sort | Farhana, Soheli |
| building | IIUM Repository |
| collection | Online Access |
| description | The interconnect and increasing chip density is still poses major threats to the continued development of
large scale binary integrated systems and implementation in VLSI using traditional binary logic system.
The design and simulation of a Multiple Valued Logic (MVL) Analog-to-Digital Converter (ADC) circuit is
presented in this paper. The ADC generates multi-valued logic outputs rather than the conventional binary
output system. The design implements pipeline ADC architecture and is simulated using the model
parameters for a standard 0.13μm CMOS process. The performance analysis of the design shows desirable
qualities in terms of response, low power consumption, and a sampling rate of 500kz at a supply voltage of
1.3 V. The ADC design is suitable for the needs of mixed-signal integrated circuit design and implemented
as a conversion circuit for systems based on multi valued logic design. |
| first_indexed | 2025-11-14T15:15:08Z |
| format | Article |
| id | iium-24248 |
| institution | International Islamic University Malaysia |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-14T15:15:08Z |
| publishDate | 2012 |
| publisher | Academic Information Press |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | iium-242482020-11-30T02:00:10Z http://irep.iium.edu.my/24248/ Design of a multiple valued logic analog to digital converter using 0.13μm CMOS process Farhana, Soheli Alam, A. H. M. Zahirul Khan, Sheroz TK Electrical engineering. Electronics Nuclear engineering The interconnect and increasing chip density is still poses major threats to the continued development of large scale binary integrated systems and implementation in VLSI using traditional binary logic system. The design and simulation of a Multiple Valued Logic (MVL) Analog-to-Digital Converter (ADC) circuit is presented in this paper. The ADC generates multi-valued logic outputs rather than the conventional binary output system. The design implements pipeline ADC architecture and is simulated using the model parameters for a standard 0.13μm CMOS process. The performance analysis of the design shows desirable qualities in terms of response, low power consumption, and a sampling rate of 500kz at a supply voltage of 1.3 V. The ADC design is suitable for the needs of mixed-signal integrated circuit design and implemented as a conversion circuit for systems based on multi valued logic design. Academic Information Press 2012-03 Article PeerReviewed application/pdf en http://irep.iium.edu.my/24248/1/Journal_SSDR.pdf Farhana, Soheli and Alam, A. H. M. Zahirul and Khan, Sheroz (2012) Design of a multiple valued logic analog to digital converter using 0.13μm CMOS process. Science Series Data Report, 4 (3). (1-8). ISSN 1307-119X http://www.ssdr.sciencerecord.com/auto/index.php/archive/part/4/3/1/?currentVol=4¤tissue=3 |
| spellingShingle | TK Electrical engineering. Electronics Nuclear engineering Farhana, Soheli Alam, A. H. M. Zahirul Khan, Sheroz Design of a multiple valued logic analog to digital converter using 0.13μm CMOS process |
| title | Design of a multiple valued logic analog to digital converter using 0.13μm CMOS process |
| title_full | Design of a multiple valued logic analog to digital converter using 0.13μm CMOS process |
| title_fullStr | Design of a multiple valued logic analog to digital converter using 0.13μm CMOS process |
| title_full_unstemmed | Design of a multiple valued logic analog to digital converter using 0.13μm CMOS process |
| title_short | Design of a multiple valued logic analog to digital converter using 0.13μm CMOS process |
| title_sort | design of a multiple valued logic analog to digital converter using 0.13μm cmos process |
| topic | TK Electrical engineering. Electronics Nuclear engineering |
| url | http://irep.iium.edu.my/24248/ http://irep.iium.edu.my/24248/ http://irep.iium.edu.my/24248/1/Journal_SSDR.pdf |