PEDES 2012 - IEEE International Conference on Power Electronics, Drives and Energy Systems

In power hardware in the loop (PHIL) simulations, a real-time simulated power system is interfaced to a piece of hardware, usually called hardware under test (HuT). A PHIL test can be realized using several simulation tools. Among them Real Time Digital Simulator (RTDS) is an ideal tool to perform c...

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Main Authors: Dargahi, M., Ghosh, Arindam, Ledwich, G., zare, F.
Other Authors: Dr Tomy Sebastian
Format: Conference Paper
Published: Institute of Electrical and Electronics Engineers ( IEEE ) 2012
Online Access:http://hdl.handle.net/20.500.11937/8914
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author Dargahi, M.
Ghosh, Arindam
Ledwich, G.
zare, F.
author2 Dr Tomy Sebastian
author_facet Dr Tomy Sebastian
Dargahi, M.
Ghosh, Arindam
Ledwich, G.
zare, F.
author_sort Dargahi, M.
building Curtin Institutional Repository
collection Online Access
description In power hardware in the loop (PHIL) simulations, a real-time simulated power system is interfaced to a piece of hardware, usually called hardware under test (HuT). A PHIL test can be realized using several simulation tools. Among them Real Time Digital Simulator (RTDS) is an ideal tool to perform complex power system simulations in near real-time. Stable operation of the entire system, along with the accuracy of simulation results are the main concerns regarding a PHIL simulation. In this paper, a simulated power network on RTDS will be interfaced to HuT through a voltage source converter (VSC). Issues around stability and other interface problems are studied and a new method to stabilize some unstable PHIL cases is proposed. PHIL simulation results in PSCAD and RSCAD are presented.
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format Conference Paper
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institution Curtin University Malaysia
institution_category Local University
last_indexed 2025-11-14T06:23:05Z
publishDate 2012
publisher Institute of Electrical and Electronics Engineers ( IEEE )
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spelling curtin-20.500.11937-89142023-02-02T07:57:37Z PEDES 2012 - IEEE International Conference on Power Electronics, Drives and Energy Systems Dargahi, M. Ghosh, Arindam Ledwich, G. zare, F. Dr Tomy Sebastian Nexteer Automotive Future Enginering In power hardware in the loop (PHIL) simulations, a real-time simulated power system is interfaced to a piece of hardware, usually called hardware under test (HuT). A PHIL test can be realized using several simulation tools. Among them Real Time Digital Simulator (RTDS) is an ideal tool to perform complex power system simulations in near real-time. Stable operation of the entire system, along with the accuracy of simulation results are the main concerns regarding a PHIL simulation. In this paper, a simulated power network on RTDS will be interfaced to HuT through a voltage source converter (VSC). Issues around stability and other interface problems are studied and a new method to stabilize some unstable PHIL cases is proposed. PHIL simulation results in PSCAD and RSCAD are presented. 2012 Conference Paper http://hdl.handle.net/20.500.11937/8914 Institute of Electrical and Electronics Engineers ( IEEE ) restricted
spellingShingle Dargahi, M.
Ghosh, Arindam
Ledwich, G.
zare, F.
PEDES 2012 - IEEE International Conference on Power Electronics, Drives and Energy Systems
title PEDES 2012 - IEEE International Conference on Power Electronics, Drives and Energy Systems
title_full PEDES 2012 - IEEE International Conference on Power Electronics, Drives and Energy Systems
title_fullStr PEDES 2012 - IEEE International Conference on Power Electronics, Drives and Energy Systems
title_full_unstemmed PEDES 2012 - IEEE International Conference on Power Electronics, Drives and Energy Systems
title_short PEDES 2012 - IEEE International Conference on Power Electronics, Drives and Energy Systems
title_sort pedes 2012 - ieee international conference on power electronics, drives and energy systems
url http://hdl.handle.net/20.500.11937/8914