Real-time high-resolution downsampling algorithm on many-core processor for spatially scalable video coding
© 2015 SPIE and IS and T. The progression toward spatially scalable video coding (SVC) solutions for ubiquitous endpoint systems introduces challenges to sustain real-time frame rates in downsampling high-resolution videos into multiple layers. In addressing these challenges, we put forward a hardwa...
| Main Authors: | , , , |
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| Format: | Journal Article |
| Published: |
S P I E - International Society for Optical Engineering
2015
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| Online Access: | http://hdl.handle.net/20.500.11937/72593 |
| _version_ | 1848762791574372352 |
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| author | Buhari, A. Ling, Huo Chong Baskaran, V. Wong, K. |
| author_facet | Buhari, A. Ling, Huo Chong Baskaran, V. Wong, K. |
| author_sort | Buhari, A. |
| building | Curtin Institutional Repository |
| collection | Online Access |
| description | © 2015 SPIE and IS and T. The progression toward spatially scalable video coding (SVC) solutions for ubiquitous endpoint systems introduces challenges to sustain real-time frame rates in downsampling high-resolution videos into multiple layers. In addressing these challenges, we put forward a hardware accelerated downsampling algorithm on a parallel computing platform. First, we investigate the principal architecture of a serial downsampling algorithm in the Joint-Scalable-Video-Model reference software to identify the performance limitations for spatially SVC. Then, a parallel multicore-based downsampling algorithm is studied as a benchmark. Experimental results for this algorithm using an 8-core processor exhibit performance speedup of 5.25× against the serial algorithm in downsampling a quantum extended graphics array at 1536p video resolution into three lower resolution layers (i.e., Full-HD at 1080p, HD at 720p, and Quarter-HD at 540p). However, the achieved speedup here does not translate into the minimum required frame rate of 15 frames per second (fps) for real-time video processing. To improve the speedup, a many-core based downsampling algorithm using the compute unified device architecture parallel computing platform is proposed. The proposed algorithm increases the performance speedup to 26.14× against the serial algorithm. Crucially, the proposed algorithm exceeds the target frame rate of 15 fps, which in turn is advantageous to the overall performance of the video encoding process. |
| first_indexed | 2025-11-14T10:53:11Z |
| format | Journal Article |
| id | curtin-20.500.11937-72593 |
| institution | Curtin University Malaysia |
| institution_category | Local University |
| last_indexed | 2025-11-14T10:53:11Z |
| publishDate | 2015 |
| publisher | S P I E - International Society for Optical Engineering |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | curtin-20.500.11937-725932018-12-13T09:33:20Z Real-time high-resolution downsampling algorithm on many-core processor for spatially scalable video coding Buhari, A. Ling, Huo Chong Baskaran, V. Wong, K. © 2015 SPIE and IS and T. The progression toward spatially scalable video coding (SVC) solutions for ubiquitous endpoint systems introduces challenges to sustain real-time frame rates in downsampling high-resolution videos into multiple layers. In addressing these challenges, we put forward a hardware accelerated downsampling algorithm on a parallel computing platform. First, we investigate the principal architecture of a serial downsampling algorithm in the Joint-Scalable-Video-Model reference software to identify the performance limitations for spatially SVC. Then, a parallel multicore-based downsampling algorithm is studied as a benchmark. Experimental results for this algorithm using an 8-core processor exhibit performance speedup of 5.25× against the serial algorithm in downsampling a quantum extended graphics array at 1536p video resolution into three lower resolution layers (i.e., Full-HD at 1080p, HD at 720p, and Quarter-HD at 540p). However, the achieved speedup here does not translate into the minimum required frame rate of 15 frames per second (fps) for real-time video processing. To improve the speedup, a many-core based downsampling algorithm using the compute unified device architecture parallel computing platform is proposed. The proposed algorithm increases the performance speedup to 26.14× against the serial algorithm. Crucially, the proposed algorithm exceeds the target frame rate of 15 fps, which in turn is advantageous to the overall performance of the video encoding process. 2015 Journal Article http://hdl.handle.net/20.500.11937/72593 10.1117/1.JEI.24.1.013025 S P I E - International Society for Optical Engineering restricted |
| spellingShingle | Buhari, A. Ling, Huo Chong Baskaran, V. Wong, K. Real-time high-resolution downsampling algorithm on many-core processor for spatially scalable video coding |
| title | Real-time high-resolution downsampling algorithm on many-core processor for spatially scalable video coding |
| title_full | Real-time high-resolution downsampling algorithm on many-core processor for spatially scalable video coding |
| title_fullStr | Real-time high-resolution downsampling algorithm on many-core processor for spatially scalable video coding |
| title_full_unstemmed | Real-time high-resolution downsampling algorithm on many-core processor for spatially scalable video coding |
| title_short | Real-time high-resolution downsampling algorithm on many-core processor for spatially scalable video coding |
| title_sort | real-time high-resolution downsampling algorithm on many-core processor for spatially scalable video coding |
| url | http://hdl.handle.net/20.500.11937/72593 |