A Three-Phase Symmetrical DC-Link Multilevel Inverter with Reduced Number of DC Sources

This paper presents a novel three-phase DC-link multilevel inverter topology with reduced number of input DC power supplies. The proposed inverter consists of series-connected half-bridge modules to generate the multilevel waveform and a simple H-bridge module, acting as a polarity generator. The in...

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Main Authors: Hasan, M., Abu-Siada, Ahmed, Dahidah, M.
Format: Journal Article
Published: IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC 2017
Online Access:http://hdl.handle.net/20.500.11937/60763
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author Hasan, M.
Abu-Siada, Ahmed
Dahidah, M.
author_facet Hasan, M.
Abu-Siada, Ahmed
Dahidah, M.
author_sort Hasan, M.
building Curtin Institutional Repository
collection Online Access
description This paper presents a novel three-phase DC-link multilevel inverter topology with reduced number of input DC power supplies. The proposed inverter consists of series-connected half-bridge modules to generate the multilevel waveform and a simple H-bridge module, acting as a polarity generator. The inverter output voltage is transferred to the load through a three-phase transformer, which facilitates a galvanic isolation between the inverter and the load. The proposed topology features many advantages when compared with the conventional multilevel inverters proposed in the literatures. These features include scalability, simple control, reduced number of DC voltage sources and less devices count. A simple sinusoidal pulse-width modulation technique is employed to control the proposed inverter. The performance of the inverter is evaluated under different loading conditions and a comparison with some existing topologies is also presented. The feasibility and effectiveness of the proposed inverter are confirmed through simulation and experimental studies using a scaled down low-voltage laboratory prototype.
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spelling curtin-20.500.11937-607632018-07-19T08:37:58Z A Three-Phase Symmetrical DC-Link Multilevel Inverter with Reduced Number of DC Sources Hasan, M. Abu-Siada, Ahmed Dahidah, M. This paper presents a novel three-phase DC-link multilevel inverter topology with reduced number of input DC power supplies. The proposed inverter consists of series-connected half-bridge modules to generate the multilevel waveform and a simple H-bridge module, acting as a polarity generator. The inverter output voltage is transferred to the load through a three-phase transformer, which facilitates a galvanic isolation between the inverter and the load. The proposed topology features many advantages when compared with the conventional multilevel inverters proposed in the literatures. These features include scalability, simple control, reduced number of DC voltage sources and less devices count. A simple sinusoidal pulse-width modulation technique is employed to control the proposed inverter. The performance of the inverter is evaluated under different loading conditions and a comparison with some existing topologies is also presented. The feasibility and effectiveness of the proposed inverter are confirmed through simulation and experimental studies using a scaled down low-voltage laboratory prototype. 2017 Journal Article http://hdl.handle.net/20.500.11937/60763 10.1109/TPEL.2017.2780849 IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC restricted
spellingShingle Hasan, M.
Abu-Siada, Ahmed
Dahidah, M.
A Three-Phase Symmetrical DC-Link Multilevel Inverter with Reduced Number of DC Sources
title A Three-Phase Symmetrical DC-Link Multilevel Inverter with Reduced Number of DC Sources
title_full A Three-Phase Symmetrical DC-Link Multilevel Inverter with Reduced Number of DC Sources
title_fullStr A Three-Phase Symmetrical DC-Link Multilevel Inverter with Reduced Number of DC Sources
title_full_unstemmed A Three-Phase Symmetrical DC-Link Multilevel Inverter with Reduced Number of DC Sources
title_short A Three-Phase Symmetrical DC-Link Multilevel Inverter with Reduced Number of DC Sources
title_sort three-phase symmetrical dc-link multilevel inverter with reduced number of dc sources
url http://hdl.handle.net/20.500.11937/60763