FPGA multi-filter system for speech enhancement via multi-criteriaoptimization

Speech is the main medium for human communication and interaction. Apart from the traditional telephones, more and more applications come with speech interfaces, which use speech signal as an input for various purposes. However, many of these applications might fail to perform in noisy environments...

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Main Authors: Yiu, C., Li, Z., Low, Siow Yong, Nordholm, Sven
Format: Journal Article
Published: Elsevier 2014
Subjects:
Online Access:http://hdl.handle.net/20.500.11937/38042
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author Yiu, C.
Li, Z.
Low, Siow Yong
Nordholm, Sven
author_facet Yiu, C.
Li, Z.
Low, Siow Yong
Nordholm, Sven
author_sort Yiu, C.
building Curtin Institutional Repository
collection Online Access
description Speech is the main medium for human communication and interaction. Apart from the traditional telephones, more and more applications come with speech interfaces, which use speech signal as an input for various purposes. However, many of these applications might fail to perform in noisy environments as the signal-to-noise ratio (SNR) degrades. Two important measures for any speech enhancement algorithm are noise suppression and speech distortion. Naturally, different speech enhancement algorithms will have different trade-offs. Moreover, depending on the environment, it is possible that one algorithm will outperform the others in some respects. This paper proposes a multi-filter system, which has the capability of continually adjusting the noise suppression level and the speech distortion level in a Pareto fashion. Moreover, we show that the system works under a variety of noisy environments and we obtain the efficient frontier of the combined filters for each background noise. Because the multi-filters are adapting in parallel, the final system can be implemented on FPGA efficiently.
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institution Curtin University Malaysia
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publishDate 2014
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spelling curtin-20.500.11937-380422018-03-29T09:07:09Z FPGA multi-filter system for speech enhancement via multi-criteriaoptimization Yiu, C. Li, Z. Low, Siow Yong Nordholm, Sven Signal enhancement Multi-criteria FPGA Speech is the main medium for human communication and interaction. Apart from the traditional telephones, more and more applications come with speech interfaces, which use speech signal as an input for various purposes. However, many of these applications might fail to perform in noisy environments as the signal-to-noise ratio (SNR) degrades. Two important measures for any speech enhancement algorithm are noise suppression and speech distortion. Naturally, different speech enhancement algorithms will have different trade-offs. Moreover, depending on the environment, it is possible that one algorithm will outperform the others in some respects. This paper proposes a multi-filter system, which has the capability of continually adjusting the noise suppression level and the speech distortion level in a Pareto fashion. Moreover, we show that the system works under a variety of noisy environments and we obtain the efficient frontier of the combined filters for each background noise. Because the multi-filters are adapting in parallel, the final system can be implemented on FPGA efficiently. 2014 Journal Article http://hdl.handle.net/20.500.11937/38042 10.1016/j.asoc.2014.03.016 Elsevier restricted
spellingShingle Signal enhancement
Multi-criteria
FPGA
Yiu, C.
Li, Z.
Low, Siow Yong
Nordholm, Sven
FPGA multi-filter system for speech enhancement via multi-criteriaoptimization
title FPGA multi-filter system for speech enhancement via multi-criteriaoptimization
title_full FPGA multi-filter system for speech enhancement via multi-criteriaoptimization
title_fullStr FPGA multi-filter system for speech enhancement via multi-criteriaoptimization
title_full_unstemmed FPGA multi-filter system for speech enhancement via multi-criteriaoptimization
title_short FPGA multi-filter system for speech enhancement via multi-criteriaoptimization
title_sort fpga multi-filter system for speech enhancement via multi-criteriaoptimization
topic Signal enhancement
Multi-criteria
FPGA
url http://hdl.handle.net/20.500.11937/38042