Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m)
This paper presents an error tolerant hardware efficient VLSI architecture for bit parallel systolic multiplication over dual base, which can be pipelined. This error tolerant architecture is well suited to VLSI implementation because of its regularity, modular structure, and unidirectional data flo...
| Main Authors: | , , , , |
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| Other Authors: | |
| Format: | Conference Paper |
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IEEE Proceeding
2009
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| Subjects: | |
| Online Access: | http://hdl.handle.net/20.500.11937/31256 |
| _version_ | 1848753327130542080 |
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| author | Singh, Ashutosh Kumar Bera, A. Rahaman, H. Mathew, J. Pradhan, D.k. |
| author2 | Long, Bing. |
| author_facet | Long, Bing. Singh, Ashutosh Kumar Bera, A. Rahaman, H. Mathew, J. Pradhan, D.k. |
| author_sort | Singh, Ashutosh Kumar |
| building | Curtin Institutional Repository |
| collection | Online Access |
| description | This paper presents an error tolerant hardware efficient VLSI architecture for bit parallel systolic multiplication over dual base, which can be pipelined. This error tolerant architecture is well suited to VLSI implementation because of its regularity, modular structure, and unidirectional data flow. The length of the largest delay path and area of this architecture are less compared to the bit parallel systolic multiplication architectures reported earlier. The architecture is implemented using Austria Micro System's 0.35um CMOS technology. This architecture can also operate over both the dual-base and polynomial base. |
| first_indexed | 2025-11-14T08:22:45Z |
| format | Conference Paper |
| id | curtin-20.500.11937-31256 |
| institution | Curtin University Malaysia |
| institution_category | Local University |
| last_indexed | 2025-11-14T08:22:45Z |
| publishDate | 2009 |
| publisher | IEEE Proceeding |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | curtin-20.500.11937-312562017-12-11T04:32:57Z Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m) Singh, Ashutosh Kumar Bera, A. Rahaman, H. Mathew, J. Pradhan, D.k. Long, Bing. error correction Finite Field systolic VLSI Testing RS codes bit parallel This paper presents an error tolerant hardware efficient VLSI architecture for bit parallel systolic multiplication over dual base, which can be pipelined. This error tolerant architecture is well suited to VLSI implementation because of its regularity, modular structure, and unidirectional data flow. The length of the largest delay path and area of this architecture are less compared to the bit parallel systolic multiplication architectures reported earlier. The architecture is implemented using Austria Micro System's 0.35um CMOS technology. This architecture can also operate over both the dual-base and polynomial base. 2009 Conference Paper http://hdl.handle.net/20.500.11937/31256 IEEE Proceeding fulltext |
| spellingShingle | error correction Finite Field systolic VLSI Testing RS codes bit parallel Singh, Ashutosh Kumar Bera, A. Rahaman, H. Mathew, J. Pradhan, D.k. Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m) |
| title | Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m) |
| title_full | Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m) |
| title_fullStr | Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m) |
| title_full_unstemmed | Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m) |
| title_short | Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m) |
| title_sort | error detecting dual basis bit parallel systolic multiplication architecture over gf(2m) |
| topic | error correction Finite Field systolic VLSI Testing RS codes bit parallel |
| url | http://hdl.handle.net/20.500.11937/31256 |