Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m)

Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m)

This paper presents an error tolerant hardware efficient VLSI architecture for bit parallel systolic multiplication over dual base, which can be pipelined. This error tolerant architecture is well suited to VLSI implementation because of its regularity, modular structure, and unidirectional data flo...

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Bibliographic Details
Main Authors: Singh, Ashutosh Kumar, Bera, A., Rahaman, H., Mathew, J., Pradhan, D.k.
Other Authors: Long, Bing.
Format: Conference Paper
Published: IEEE Proceeding 2009
Subjects:
error correction
Finite Field
systolic
VLSI Testing
RS codes
bit parallel
Online Access:http://hdl.handle.net/20.500.11937/31256
Description
Summary:This paper presents an error tolerant hardware efficient VLSI architecture for bit parallel systolic multiplication over dual base, which can be pipelined. This error tolerant architecture is well suited to VLSI implementation because of its regularity, modular structure, and unidirectional data flow. The length of the largest delay path and area of this architecture are less compared to the bit parallel systolic multiplication architectures reported earlier. The architecture is implemented using Austria Micro System's 0.35um CMOS technology. This architecture can also operate over both the dual-base and polynomial base.

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