APA (7th ed.) Citation

Singh, A. K., Bera, A., Rahaman, H., Mathew, J., Pradhan, D., & Long, B. (2009). Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m). IEEE Proceeding.

Chicago Style (17th ed.) Citation

Singh, Ashutosh Kumar, A. Bera, H. Rahaman, J. Mathew, D.k Pradhan, and Bing Long. Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m). IEEE Proceeding, 2009.

MLA (9th ed.) Citation

Singh, Ashutosh Kumar, et al. Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m). IEEE Proceeding, 2009.