A neural model for processor-throughput using hardware parameters and software's dynamic behavior
Design space exploration of a processor system, prior to its hardware implementation, usually involves cycle-accurate simulations. The simulations provide a good measure of performance but require long periods of time even when a small set of design variations are assessed. An alternative is to use...
| Main Authors: | , , , |
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| Other Authors: | |
| Format: | Conference Paper |
| Published: |
Institute of Electrical and Electronics Engineers ( IEEE )
2012
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| Online Access: | http://hdl.handle.net/20.500.11937/26355 |
| _version_ | 1848751963173289984 |
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| author | Beg, A. Prasad, P.C. Singh, Ashutosh Kumar Senananayake, A. |
| author2 | Abraham, A. |
| author_facet | Abraham, A. Beg, A. Prasad, P.C. Singh, Ashutosh Kumar Senananayake, A. |
| author_sort | Beg, A. |
| building | Curtin Institutional Repository |
| collection | Online Access |
| description | Design space exploration of a processor system, prior to its hardware implementation, usually involves cycle-accurate simulations. The simulations provide a good measure of performance but require long periods of time even when a small set of design variations are assessed. An alternative is to use empirically-developed models which are much faster than actual simulations. In this paper, we have proposed an NN model for processor performance (IPC) prediction. The model uses a larger set of input parameters (especially the software parameters) than the prior models. For dimension reduction, we found PCA to be a more useful technique than correlation and graphical analysis. For the purpose of training the NNs, we used the data from a large number of simulations of industry-standard SPEC CPU 2000 and SPEC CPU 2006 benchmark suites In order to collect the NN training data in a reasonable period of time, we utilized two well-known techniques, namely, benchmark-subsetting and SPs. |
| first_indexed | 2025-11-14T08:01:04Z |
| format | Conference Paper |
| id | curtin-20.500.11937-26355 |
| institution | Curtin University Malaysia |
| institution_category | Local University |
| last_indexed | 2025-11-14T08:01:04Z |
| publishDate | 2012 |
| publisher | Institute of Electrical and Electronics Engineers ( IEEE ) |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | curtin-20.500.11937-263552023-02-02T07:57:40Z A neural model for processor-throughput using hardware parameters and software's dynamic behavior Beg, A. Prasad, P.C. Singh, Ashutosh Kumar Senananayake, A. Abraham, A. Zomaya, A. Ventura, S. Yager, R. Snasel, V. Muda, A.K. Samuel, P. Design space exploration of a processor system, prior to its hardware implementation, usually involves cycle-accurate simulations. The simulations provide a good measure of performance but require long periods of time even when a small set of design variations are assessed. An alternative is to use empirically-developed models which are much faster than actual simulations. In this paper, we have proposed an NN model for processor performance (IPC) prediction. The model uses a larger set of input parameters (especially the software parameters) than the prior models. For dimension reduction, we found PCA to be a more useful technique than correlation and graphical analysis. For the purpose of training the NNs, we used the data from a large number of simulations of industry-standard SPEC CPU 2000 and SPEC CPU 2006 benchmark suites In order to collect the NN training data in a reasonable period of time, we utilized two well-known techniques, namely, benchmark-subsetting and SPs. 2012 Conference Paper http://hdl.handle.net/20.500.11937/26355 10.1109/ISDA.2012.6416643 Institute of Electrical and Electronics Engineers ( IEEE ) restricted |
| spellingShingle | Beg, A. Prasad, P.C. Singh, Ashutosh Kumar Senananayake, A. A neural model for processor-throughput using hardware parameters and software's dynamic behavior |
| title | A neural model for processor-throughput using hardware parameters and software's dynamic behavior |
| title_full | A neural model for processor-throughput using hardware parameters and software's dynamic behavior |
| title_fullStr | A neural model for processor-throughput using hardware parameters and software's dynamic behavior |
| title_full_unstemmed | A neural model for processor-throughput using hardware parameters and software's dynamic behavior |
| title_short | A neural model for processor-throughput using hardware parameters and software's dynamic behavior |
| title_sort | neural model for processor-throughput using hardware parameters and software's dynamic behavior |
| url | http://hdl.handle.net/20.500.11937/26355 |